| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 04/17/2001 | US6219287 Fail memory circuit and interleave copy method of the same |
| 04/17/2001 | US6219284 Programmable logic device with multi-port memory |
| 04/17/2001 | US6219283 Memory device with local write data latches |
| 04/17/2001 | US6219278 Sense amplifier for memory |
| 04/17/2001 | US6219269 Semiconductor memory device capable of improving read operation speed |
| 04/17/2001 | US6219160 Optical logic element and methods for respectively its preparation and optical addressing, as well as the use thereof in an optical logic device |
| 04/17/2001 | US6217213 Temperature sensing systems and methods |
| 04/12/2001 | WO2001026139A2 Dram bit lines and support circuitry contacting scheme |
| 04/12/2001 | WO2001026115A1 Semiconductor integrated circuit, ink cartridge having this semiconductor integrated circuit, and ink jet recording device mounted with this ink cartridge |
| 04/12/2001 | WO2001026113A1 Integrated circuit with a non-volatile mos ram cell |
| 04/12/2001 | WO2001025955A1 Portable digital audio device |
| 04/12/2001 | WO2000060599A3 Electronic cassette apparatus and method |
| 04/12/2001 | DE19940905A1 Tonwiedergabe- und Tonaufzeichnungsvorrichtung Sound recording and sound reproduction |
| 04/12/2001 | DE10049934A1 Integrated circuit component has memory cell fields, pipeline block with sampling amplifiers used in common by memory cell fields, to which they are coupled via input/output lines |
| 04/12/2001 | DE10049036A1 Recording and replay device for main- and auxiliary-data e.g. for multi-media card or PC-card, uses control device for recording and/or replay device to ensure recording of main data |
| 04/12/2001 | DE10049029A1 Circuit for determining latency of buffer circuit generates latency interval and latency indication from clock signal and from test signal derived from clock signal with delay |
| 04/12/2001 | DE10034231A1 Sense amplifier circuit for semiconductor memory has first and second load transistors respectively connected to first and second data lines to provide charging currents to data lines |
| 04/11/2001 | EP1023731A4 Sense amplifier for flash memories |
| 04/11/2001 | CN1291325A Reproducing apparatus and recording and reproducing apparatus |
| 04/11/2001 | CN1290891A Device, method and system for read/write data and medium for providing data read/write program |
| 04/10/2001 | US6216246 Methods to make DRAM fully compatible with SRAM using error correction code (ECC) mechanism |
| 04/10/2001 | US6216180 Method and apparatus for a nonvolatile memory interface for burst read operations |
| 04/10/2001 | US6215837 Pipe counter signal generator processing double data in semiconductor device |
| 04/10/2001 | US6215729 Programmable counter circuit for generating a sequential/interleave address sequence |
| 04/10/2001 | US6215728 Data storage device capable of storing plural bits of data |
| 04/10/2001 | US6215727 Method and apparatus for utilizing parallel memory in a serial memory system |
| 04/10/2001 | US6215726 Semiconductor device with internal clock generating circuit capable of generating internal clock signal with suppressed edge-to-edge jitter |
| 04/10/2001 | US6215725 Clock-synchronized memory |
| 04/10/2001 | US6215724 Circuit and method for eliminating idle cycles in a memory device |
| 04/10/2001 | US6215722 Command latency circuit for programmable SLDRAM and latency control method therefor |
| 04/10/2001 | US6215721 Multi-bank memory device and method for arranging input/output lines |
| 04/10/2001 | US6215720 High speed operable semiconductor memory device with memory blocks arranged about the center |
| 04/10/2001 | US6215719 Memory device having line address counter for making next line active while current line is processed |
| 04/10/2001 | US6215718 Architecture for large capacity high-speed random access memory |
| 04/10/2001 | US6215717 Semiconductor memory device for reducing a time needed for performing a protecting operation |
| 04/10/2001 | US6215716 Static memory cell having independent data holding voltage |
| 04/10/2001 | US6215713 Bitline amplifier having improved response |
| 04/10/2001 | US6215711 Row address strobe signal generating device |
| 04/10/2001 | US6215710 Apparatus and method for controlling data strobe signal in DDR SDRAM |
| 04/10/2001 | US6215709 Synchronous dynamic random access memory device |
| 04/10/2001 | US6215706 Fast structure dram |
| 04/10/2001 | US6215690 Semiconductor memory devices having shared data line contacts |
| 04/10/2001 | US6215349 Capacitive coupled driver circuit |
| 04/10/2001 | US6215331 Method and apparatus for separately controlling the sensing and reset phases of a sense amp/regenerative latch |
| 04/10/2001 | US6215329 Output stage for a memory device and for low voltage applications |
| 04/05/2001 | WO2001024263A1 Reducing impact of coupling noise in signal lines |
| 04/05/2001 | WO2001024189A1 Zero power sram precharge |
| 04/05/2001 | WO2001024184A1 Configurable synchronizer for double data rate synchronous dynamic random access memory |
| 04/05/2001 | WO2001024041A1 Automatic selection of recording mode in portable digital audio recorder |
| 04/05/2001 | DE19942941A1 Signalverstärker einer Ausleseeinrichtung für Speicherleuchtstoffplatten Signal amplifier readout means for storage phosphor plates |
| 04/05/2001 | DE10047451A1 Data output circuit for semiconductor component, has output driver unit to pass output driver event in response to output of level shifter circuit after maintaining data output connection in high impedance state |
| 04/04/2001 | EP1089290A1 Memory with column register and writing method |
| 04/04/2001 | EP1089289A1 Serial access integrated memory circuit |
| 04/04/2001 | EP1089286A1 Clock suspending circuitry |
| 04/04/2001 | EP1089285A1 Method of strobing a sense amplifier |
| 04/04/2001 | EP1089218A1 Input circuit for memory IC card |
| 04/03/2001 | US6212615 Semiconductor circuit having burst counter circuit which is reduced the circuits passing from the clock input terminal to output terminal |
| 04/03/2001 | US6212607 Multi-ported memory architecture using single-ported RAM |
| 04/03/2001 | US6212596 Synchronous memory and data processing system having a programmable burst length |
| 04/03/2001 | US6212127 Semiconductor device and timing control circuit |
| 04/03/2001 | US6212126 Semiconductor device including clock generation circuit capable of generating internal clock stably |
| 04/03/2001 | US6212125 Asynchronous semiconductor memory device with a control circuit that controls the latch timing of an input signal |
| 04/03/2001 | US6212122 Dual port memory operation method with synchronized read and write pointers |
| 04/03/2001 | US6212120 Semiconductor memory device with less power consumption |
| 04/03/2001 | US6212117 Duplicate bitline self-time technique for reliable memory operation |
| 04/03/2001 | US6212116 Semiconductor memory device |
| 04/03/2001 | US6212111 Synchronous dynamic random access memory device |
| 04/03/2001 | US6212110 Semiconductor memory device |
| 04/03/2001 | US6212109 Dynamic memory array having write data applied to selected bit line sense amplifiers before sensing to write associated selected memory cells |
| 04/03/2001 | US6212108 Distributed voltage charge circuits to reduce sensing time in a memory device |
| 04/03/2001 | US6212097 Nonvolatile memory |
| 04/03/2001 | US6212092 Semiconductor integrated circuit |
| 04/03/2001 | US6212091 Semiconductor memory device having a shielding line |
| 04/03/2001 | US6211700 Data transfer device with a post charge logic |
| 03/29/2001 | WO2001022423A1 Memory devices |
| 03/29/2001 | DE10043650A1 Internal clock generation circuit for SDRAM, has delay circuits to delay internal signals based on delay control time set according to phase difference between one of the internal signals and output of delay circuit |
| 03/28/2001 | EP1086465A1 Method and apparatus for a serial access memory |
| 03/28/2001 | EP0925548B1 Data transfer method for a radio frequency identification system |
| 03/28/2001 | CN1289126A Semiconductor apparatus |
| 03/27/2001 | US6209071 Asynchronous request/synchronous data dynamic random access memory |
| 03/27/2001 | US6209056 Semiconductor memory device having a plurality of bank sections distributed in a plurality of divided memory cell arrays |
| 03/27/2001 | US6209055 Method and apparatus for reducing noise induced among conductive lines |
| 03/27/2001 | US6208583 Synchronous semiconductor memory having an improved reading margin and an improved timing control in a test mode |
| 03/27/2001 | US6208582 Memory device including a double-rate input/output circuit |
| 03/27/2001 | US6208580 Semiconductor storage device including column pre-decoder circuit for preventing multiple selection of bit lines |
| 03/27/2001 | US6208576 Synchronous semiconductor memory device |
| 03/27/2001 | US6208575 Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage |
| 03/27/2001 | US6208574 Sense amplifier with local column read amplifier and local data write drivers |
| 03/27/2001 | US6208566 Semiconductor integrated circuit |
| 03/27/2001 | US6208563 Semiconductor memory device which continuously performs read/write operations with short access time |
| 03/27/2001 | US6208560 Nonvolatile semiconductor memory device |
| 03/27/2001 | US6208168 Output driver circuits having programmable pull-up and pull-down capability for driving variable loads |
| 03/23/2001 | CA2314248A1 Data bus memory circuit |
| 03/22/2001 | WO2001020615A1 High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes |
| 03/22/2001 | WO2001020611A2 Controlling burst sequence in synchronous memories |
| 03/22/2001 | DE19944040A1 Integrated memory e.g. double data rate synchronous dynamic random access memory |
| 03/22/2001 | DE10031433A1 Memory Device with Packet Command Memory device with Packet Command |
| 03/22/2001 | DE10018988A1 Pipeline device for SDRAM, includes register which supply data to corresponding data path in response to control signal output by control signal generation circuit |
| 03/22/2001 | DE10017070A1 Buffer circuit for semiconductor memory has control signal generator which produces control signal based on output signals of two pull=down switch circuits that individually turn into respective states |
| 03/21/2001 | EP1085516A2 Semiconductor storing apparatus and operation setting method of the same |