| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 08/15/2000 | US6104654 High speed sensing of dual port static RAM cell |
| 08/15/2000 | US6104653 Equilibration circuit and method using a pulsed equilibrate signal and a level equilibrate signal |
| 08/15/2000 | US6104652 Method and memory device for dynamic cell plate sensing with AC equilibrate |
| 08/15/2000 | US6104649 Semiconductor memory device |
| 08/15/2000 | US6104648 Semiconductor memory device having a large band width and allowing efficient execution of redundant repair |
| 08/15/2000 | US6104647 Semiconductor device having redundancy circuit |
| 08/15/2000 | US6104644 Circuit for the detection of changes of address |
| 08/15/2000 | US6104643 Integrated circuit clock input buffer |
| 08/15/2000 | US6104641 Switchable multi bit semiconductor memory device |
| 08/15/2000 | US6104635 Non-volatile memory device readable write data latch, and internal control thereof |
| 08/15/2000 | US6104627 Semiconductor memory device |
| 08/15/2000 | US6104626 Analog value memory circuit |
| 08/15/2000 | US6104234 Substrate voltage generation circuit |
| 08/15/2000 | US6104225 Semiconductor device using complementary clock and signal input state detection circuit used for the same |
| 08/15/2000 | US6104224 Delay circuit device having a reduced current consumption |
| 08/15/2000 | US6104209 Low skew differential receiver with disable feature |
| 08/09/2000 | EP1026695A1 Inhibiting bias buildup in memories |
| 08/09/2000 | EP1026694A1 Improved sense amplifier |
| 08/09/2000 | EP1026693A1 Dual slope sense clock generator |
| 08/09/2000 | EP1026692A2 Data output buffers in semiconductor memory devices |
| 08/09/2000 | EP1025644A1 A master-slave delay locked loop for accurate delay of non-periodic signals |
| 08/09/2000 | EP1025566A2 Rom and dram fabricated using a dram process |
| 08/09/2000 | EP1025565A1 High speed memory self-timing circuitry and methods for implementing the same |
| 08/09/2000 | EP1025564A1 Programmable logic device memory cell circuit |
| 08/09/2000 | CN1055346C 动态随机存取存储器 Dynamic Random Access Memory |
| 08/08/2000 | US6101579 Multi-port memory device having masking registers |
| 08/08/2000 | US6101329 System for comparing counter blocks and flag registers to determine whether FIFO buffer can send or receive data |
| 08/08/2000 | US6101197 Method and apparatus for adjusting the timing of signals over fine and coarse ranges |
| 08/08/2000 | US6101152 Method of operating a synchronous memory device |
| 08/08/2000 | US6101151 Synchronous semiconductor memory device employing temporary data output stop scheme |
| 08/08/2000 | US6101146 Semiconductor integrated circuit device |
| 08/08/2000 | US6101145 Sensing circuit and method |
| 08/08/2000 | US6101144 Integrated circuit memory devices having automatically induced standby modes and methods of operating same |
| 08/08/2000 | US6101142 Power up initialization circuit responding to an input signal |
| 08/08/2000 | US6101141 Integrated memory |
| 08/08/2000 | US6101140 Sense amplifier driver circuit for supplying a reduced driving voltage to sense amplifier |
| 08/08/2000 | US6101136 Signal delay device for use in semiconductor storage device for improved burst mode operation |
| 08/08/2000 | US6101135 Semiconductor memory device and data processing methods thereof |
| 08/08/2000 | US6101134 Method and circuitry for writing data |
| 08/08/2000 | US6101133 Apparatus and method for preventing accidental writes from occurring due to simultaneous address and write enable transitions |
| 08/08/2000 | US6101132 Block RAM with reset |
| 08/08/2000 | US6101127 Operating voltage selection circuit for non-volatile semiconductor memories |
| 08/08/2000 | US6101124 Memory block for realizing semiconductor memory devices and corresponding manufacturing process |
| 08/08/2000 | US6100739 Self-timed synchronous pulse generator with test mode |
| 08/08/2000 | US6100733 Clock latency compensation circuit for DDR timing |
| 08/08/2000 | CA2186312C Ink jet print head identification circuit with serial out, dynamic shift registers |
| 08/06/2000 | CA2297878A1 Synchronous memory |
| 08/03/2000 | WO2000045392A1 Integrated memory and corresponding operating method |
| 08/03/2000 | WO1999010792A3 Integrated dram with high speed interleaving |
| 08/03/2000 | DE19963684A1 Verzögerungs-Verriegelungsschleifen-Taktgenerator, welcher Verzögerungs-Impuls-Verzögerungsumwandlung einsetzt Delay-locked loop clock generator which delay pulse delay conversion uses |
| 08/02/2000 | EP1024599A2 Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays |
| 08/02/2000 | EP1023731A1 Sense amplifier for flash memories |
| 08/02/2000 | EP0677192B1 Multiple block mode operations in a frame buffer system designed for windowing operations |
| 08/01/2000 | US6098145 Pulsed Y-decoders for improving bitline precharging in memories |
| 08/01/2000 | US6097667 Synchronous memory with programmable read latency |
| 08/01/2000 | US6097663 Semiconductor IC device having a memory and a logic circuit implemented with a single chip |
| 08/01/2000 | US6097661 Pointer circuit with low surface requirement high speed and low power loss |
| 08/01/2000 | US6097659 Power-up circuit for semiconductor memory device |
| 08/01/2000 | US6097657 Method for reading out the contents of a serial memory |
| 08/01/2000 | US6097653 Circuit and method for selectively overdriving a sense amplifier |
| 08/01/2000 | US6097652 Integrated circuit memory devices including circuits and methods for discharging isolation control lines into a reference voltage |
| 08/01/2000 | US6097651 Precharge circuitry in RAM circuit |
| 08/01/2000 | US6097650 Circuit apparatus for evaluating the data content of memory cells |
| 08/01/2000 | US6097642 Bus-line midpoint holding circuit for high speed memory read operation |
| 08/01/2000 | US6097640 Memory and circuit for accessing data bits in a memory array in multi-data rate operation |
| 08/01/2000 | US6097634 Latch-type sensing circuit and program-verify circuit |
| 08/01/2000 | US6097633 Read circuit for non-volatile memories |
| 08/01/2000 | US6097432 Sense amplifier for high-density imaging array |
| 08/01/2000 | US6097242 Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits |
| 08/01/2000 | US6097216 Integrated buffer circuits having improved noise immunity and TTL-to-CMOS signal conversion capability |
| 07/26/2000 | EP1022744A1 Charge sharing circuit for fanout buffer |
| 07/26/2000 | EP1022642A1 Integrated circuit I/O using a high performance bus interface |
| 07/26/2000 | EP1022641A1 Integrated circuit i/o using a high performance bus interface |
| 07/26/2000 | EP1022628A1 Read-only sequence controller having a gate array composition |
| 07/26/2000 | EP1021807A2 Apparatus and method for simplified analog signal record and playback |
| 07/26/2000 | EP0897579B1 Memory device |
| 07/26/2000 | CN2389409Y Universal mutli-language electronic explaining apparatus |
| 07/26/2000 | CN1261455A Synchronous page-mode non-volatile memory |
| 07/26/2000 | CN1054940C Data output buffer of a synchronousemiconductor memory device |
| 07/25/2000 | US6094727 Method and apparatus for controlling the data rate of a clocking circuit |
| 07/25/2000 | US6094704 Memory device with pipelined address path |
| 07/25/2000 | US6094703 Synchronous SRAM having pipelined memory access enable for a burst of addresses |
| 07/25/2000 | US6094701 Semiconductor memory device |
| 07/25/2000 | US6094697 Information processing system including processing device for detecting non-conductivity of state-indicating non-conductive member and discriminating prohibit state of writing information to information writable storage medium |
| 07/25/2000 | US6094693 Information recording apparatus using erasure units |
| 07/25/2000 | US6094436 Integrated multiport switch having shared media access control circuitry |
| 07/25/2000 | US6094399 Fully synchronous pipelined RAM |
| 07/25/2000 | US6094398 DRAM including an address space divided into individual blocks having memory cells activated by row address signals |
| 07/25/2000 | US6094396 Memory array architecture for multi-data rate operation |
| 07/25/2000 | US6094394 Sense amplifier for non-volatile memory devices |
| 07/25/2000 | US6094393 Stacked sense-amp cache memory system and method |
| 07/25/2000 | US6094392 Semiconductor memory device |
| 07/25/2000 | US6094390 Semiconductor memory device with column gate and equalizer circuitry |
| 07/25/2000 | US6094385 Repairable memory cell for a memory cell array |
| 07/25/2000 | US6094380 Memory device with a data output buffer and the control method thereof |
| 07/25/2000 | US6094379 Memory reading circuit and SRAM |
| 07/25/2000 | US6094378 System for improved memory cell access |
| 07/25/2000 | US6094376 Data output buffer control circuit for a semiconductor memory device |
| 07/25/2000 | US6094375 Integrated circuit memory devices having multiple data rate mode capability and methods of operating same |
| 07/25/2000 | US6094104 Voltage and temperature compensated ring oscillator frequency stabilizer |