| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 06/05/2001 | US6243302 Apparatus for outputting data using common pull-up/pull-down lines with reduced load |
| 06/05/2001 | US6243291 Two-stage pipeline sensing for page mode flash memory |
| 06/05/2001 | US6243279 Semiconductor integrated circuit device |
| 06/05/2001 | US6242973 Bootstrapped CMOS driver |
| 06/05/2001 | US6242940 Data input buffer circuit |
| 05/31/2001 | WO2001039196A1 Memory device |
| 05/31/2001 | US20010002181 Data buffer control circuits, integrated circuit memory devices and methods of operation thereof using read cycle initiated data buffer clock signals |
| 05/31/2001 | US20010002179 LSI device with memory and logics mounted thereon |
| 05/31/2001 | US20010002178 Destructive read type memory circuit, restoring circuit for the same and sense amplifier |
| 05/31/2001 | US20010002177 Semiconductor device |
| 05/31/2001 | US20010002176 Semiconductor memory device having a large band width and allowing efficient execution of redundant repair |
| 05/31/2001 | US20010002172 Nonvolatile semiconductor memory device |
| 05/31/2001 | US20010002110 Current sense amplifier and current comparator with hysteresis |
| 05/31/2001 | DE19956240A1 Read and refresh control method for DRAM memory used in a microcontroller system, involves periodic refreshing of DRAM during specified wait periods of CPU |
| 05/31/2001 | DE19955779A1 Data storage device especially semiconductor memory, such as RAM or ROM |
| 05/31/2001 | DE10054141A1 Delay control circuit for synchronous dynamic direct access memory has delay model for delaying external clock signal according to asymmetry, control signal generator, two delay devices |
| 05/30/2001 | EP1104107A2 Clamp circuit for a switch |
| 05/30/2001 | EP1103979A1 Dynamic random access memory (DRAM) and reading method thereof |
| 05/30/2001 | EP1103978A1 Non-volatile memory device with burst mode reading and corresponding reading method |
| 05/30/2001 | EP1103977A1 Method for reading data from a non-volatile memory device with autodetect burst mode reading and corresponding reading circuit |
| 05/30/2001 | EP1103968A1 Apparatus for reproducing audio data, like recorded audio data, and mountable on a car |
| 05/29/2001 | US6240495 Memory control system and memory control method |
| 05/29/2001 | US6240049 Synchronous semiconductor storage device |
| 05/29/2001 | US6240048 Synchronous type semiconductor memory system with less power consumption |
| 05/29/2001 | US6240047 Synchronous dynamic random access memory with four-bit data prefetch |
| 05/29/2001 | US6240046 Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle |
| 05/29/2001 | US6240045 Synchronous semiconductor integrated circuit capable of improving immunity from malfunctions |
| 05/29/2001 | US6240043 SDRAM with a maskable input |
| 05/29/2001 | US6240042 Output circuit for a double data rate dynamic random access memory, double data rate dynamic random access memory, method of clocking data out from a double data rate dynamic random access memory and method of providing a data strobe signal |
| 05/29/2001 | US6240038 Low area impact technique for doubling the write data bandwidth of a memory array |
| 05/29/2001 | US6240031 Memory architecture |
| 05/29/2001 | US6240030 Integrated circuit devices having mode selection circuits that generate a mode signal based on the magnitude of a mode control signal when a power supply signal transitions from a first state to a second state |
| 05/29/2001 | US6240028 Simplified peripheral logic for memory device |
| 05/29/2001 | US6240024 Method and apparatus for generating an echo clock in a memory |
| 05/29/2001 | US6240018 Nonvolatile semiconductor memory device having verify function |
| 05/29/2001 | US6240005 Sense amplifier configuration with fused diffusion regions and a distributed driver system |
| 05/29/2001 | US6239958 Electrostatic damage protection circuit and dynamic random access memory |
| 05/29/2001 | US6239647 Decoder circuit and decoding method of the same |
| 05/29/2001 | US6239635 Self-timing control circuit |
| 05/29/2001 | US6239633 Digital DLL circuit |
| 05/29/2001 | US6239624 Low-power sense amplifier for memory |
| 05/25/2001 | WO2001037282A1 Digital recording and playback system |
| 05/24/2001 | US20010001601 Delayed locked loop implementation in a synchronous dynamic random access memory |
| 05/24/2001 | US20010001598 Dynamic random access memory (RAM), semiconductor storage device, and semiconductor integrated circuit (IC) device |
| 05/23/2001 | EP0928484B1 Charge sharing detection circuit for anti-fuses |
| 05/23/2001 | DE19952947A1 Register information read out device e.g. for semiconductor chip identification |
| 05/23/2001 | DE10053906A1 Synchronous mask ROM component has word decoder that holds word signal while internal clock signal is deactivated, and which outputs control signal for transferring read data |
| 05/23/2001 | CN1296624A Semiconductor memory asynchronous pipeline |
| 05/23/2001 | CN1296265A Copy protection for system software embedded in nonvolatic storage device |
| 05/22/2001 | US6236619 Synchronous dynamic random access memory semiconductor device having write-interrupt-write function |
| 05/22/2001 | US6236616 Semiconductor memory device having data input/output line shared by a plurality of banks |
| 05/22/2001 | US6236613 Semiconductor integrated circuit device having a hierarchical power source configuration |
| 05/22/2001 | US6236612 Integrated semiconductor memory configuration with self-buffering of supply voltages |
| 05/22/2001 | US6236606 Row decoded biasing of sense amplifier for improved one's margin |
| 05/22/2001 | US6236605 Semiconductor integrated circuit and semiconductor memory device including overdriving sense amplifier |
| 05/22/2001 | US6236603 High speed charging of core cell drain lines in a memory device |
| 05/22/2001 | US6236602 Dynamic configuration of storage arrays |
| 05/22/2001 | US6236601 Semiconductor memory device having faulty cells |
| 05/22/2001 | US6236600 Inhibiting memory data burn-in |
| 05/22/2001 | US6236251 Semiconductor integrated circuit with multiple selectively activated synchronization circuits |
| 05/17/2001 | WO2001035419A1 Simultaneous addressing using single-port rams |
| 05/17/2001 | US20010001262 Semiconductor device |
| 05/17/2001 | US20010001261 Circuit for resetting a pair of data buses of a semiconductor memory device |
| 05/17/2001 | US20010001206 Set of two memories on the same monolithic integrated circuit |
| 05/16/2001 | EP1100090A1 Synchronous LSI memory device |
| 05/16/2001 | CN1295332A MRAM device having digital detection amplifier |
| 05/15/2001 | US6233694 Synchronization device for synchronous dynamic random-access memory |
| 05/15/2001 | US6233199 Full page increment/decrement burst for DDR SDRAM/SGRAM |
| 05/15/2001 | US6233197 Multi-port semiconductor memory and compiler having capacitance compensation |
| 05/15/2001 | US6233196 Multi-bank integrated circuit memory devices with diagonal pairs of sub-banks |
| 05/15/2001 | US6233191 Field programmable memory array |
| 05/15/2001 | US6233190 Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit |
| 05/15/2001 | US6233188 Precharge control signal generating circuit |
| 05/15/2001 | US6233187 Semiconductor memory device |
| 05/15/2001 | US6233186 Memory device having reduced precharge time |
| 05/15/2001 | US6233180 Device for determining the validity of word line conditions and for delaying data sensing operation |
| 05/15/2001 | US6233179 Circuit and method for reading and writing data in a memory device |
| 05/15/2001 | US6233170 Sense amplifier circuit, memory device using the circuit and method for reading the memory device |
| 05/15/2001 | US6232812 Integrated circuit delay lines having programmable and phase matching delay characteristics |
| 05/15/2001 | US6232801 Comparators and comparison methods |
| 05/15/2001 | US6232800 Differential sense amplifier circuit and dynamic logic circuit using the same |
| 05/15/2001 | US6232797 Integrated circuit devices having data buffer control circuitry therein that accounts for clock irregularities |
| 05/15/2001 | US6232796 Apparatus and method for detecting two data bits per clock edge |
| 05/15/2001 | US6231147 Data storage circuits using a low threshold voltage output enable circuit |
| 05/10/2001 | US20010000994 Semiconductor device reconciling different timing signals |
| 05/10/2001 | US20010000991 Semiconductor memory device |
| 05/10/2001 | US20010000949 Integrated circuit memory devices having programmable output driver circuits therein |
| 05/10/2001 | DE10037973A1 Data output circuit has buffer stage containing pull-up and pull-down transistors, high and low level data output control stages and substrate potential switching stage |
| 05/09/2001 | EP1097455A1 Method and apparatus for controlling the data rate of a clocking circuit |
| 05/09/2001 | EP0789917B1 Method and structure for controlling internal operations of a dram array |
| 05/09/2001 | CN1294709A Circuit for powering down unused configuration bits to minimize power consumption |
| 05/08/2001 | US6230280 Synchronous semiconductor memory device capable of generating stable internal voltage |
| 05/08/2001 | US6230275 Circuit for powering down unused configuration bits to minimize power consumption |
| 05/08/2001 | US6230250 Synchronous memory and data processing system having a programmable burst order |
| 05/08/2001 | US6230245 Method and apparatus for generating a variable sequence of memory device command signals |
| 05/08/2001 | US6230244 Memory device with read access controlled by code |
| 05/08/2001 | US6229759 Semiconductor memory burst length count determination method |
| 05/08/2001 | US6229758 Semiconductor memory device that can read out data faster than writing it |
| 05/08/2001 | US6229757 Semiconductor memory device capable of securing large latch margin |
| 05/08/2001 | US6229756 Semiconductor memory device capable of preventing mis-operation due to load of column address line |