| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
|---|
| 09/11/2001 | US6288959 Controlling the precharge operation in a DRAM array in a SRAM interface |
| 09/11/2001 | US6288953 Semiconductor memory device having sense amplifier control circuit responding to an address transition detection circuit |
| 09/11/2001 | US6288952 System for improved memory cell access |
| 09/11/2001 | US6288947 Data output apparatus guaranteeing complete data transfer using delayed time in memory device having pipelatch circuits |
| 09/11/2001 | US6288945 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| 09/11/2001 | US6288939 Circuit configuration for monitoring states of a memory device |
| 09/11/2001 | US6288928 Semiconductor integrated circuit and method of controlling column switch of semiconductor integrated circuit in write operation |
| 09/11/2001 | US6288927 Semiconductor memory device with column gate and equalizer circuitry |
| 09/11/2001 | US6288925 System with meshed power and signal buses on cell array |
| 09/11/2001 | US6288585 Semiconductor device using external power voltage for timing sensitive signals |
| 09/11/2001 | US6288575 Pseudo-differential current sense amplifier with hysteresis |
| 09/11/2001 | CA2217375C Bi-directional data bus scheme with optimized read and write characteristics |
| 09/07/2001 | WO2001065562A1 Data balancing scheme in solid state storage devices |
| 09/06/2001 | US20010020095 High affinity for D4 receptors; treatment of schizophrenia, other psychoses, anxiety disorders, depression, alcohol abuse, impulse control disorders, aggression |
| 09/06/2001 | US20010019556 High speed programmable counter |
| 09/06/2001 | US20010019514 Use of setup time to send signal through die |
| 09/06/2001 | US20010019512 Semiconductor memory device having large data I/O width and capable of speeding up data input/output and reducing power consumption |
| 09/06/2001 | US20010019505 Method and apparatus for alternate operation of a random access memory in single-memory operating mode and in combined multi-memory operating mode |
| 09/06/2001 | US20010019504 DRAM circuit and method of controlling the same |
| 09/06/2001 | US20010019503 Clock synchronous semiconductor memory device having a reduced access time |
| 09/06/2001 | US20010019502 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 09/06/2001 | US20010019283 High-speed dynamic latch |
| 09/06/2001 | US20010019139 Circuit configuration for an integrated semiconductor memory with column access |
| 09/05/2001 | EP1130778A2 Semiconductor register element |
| 09/05/2001 | EP1130603A2 Dynamic random access memory device with enhanced bus turnaround |
| 09/05/2001 | EP1130601A1 Column decoder circuit for page reading of a semiconductor memory |
| 09/05/2001 | EP1130600A1 Data balancing scheme in solid state storage devices |
| 09/04/2001 | US6286077 Synchronous semiconductor memory device with a plurality of memory modules which has an additional function for masking a data strobe signal outputted from each memory module |
| 09/04/2001 | US6286076 High speed memory-based buffer and system and method for use thereof |
| 09/04/2001 | US6285723 Timing signal generation circuit |
| 09/04/2001 | US6285626 Semiconductor device |
| 09/04/2001 | US6285625 High-speed clock circuit for semiconductor memory device |
| 09/04/2001 | US6285624 Multilevel memory access method |
| 09/04/2001 | US6285623 Semiconductor memory |
| 09/04/2001 | US6285618 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array |
| 09/04/2001 | US6285615 Multiple output current mirror with improved accuracy |
| 09/04/2001 | US6285613 Semiconductor memory device |
| 09/04/2001 | US6285611 Memory device having input and output sense amplifiers that occupy less circuit area |
| 09/04/2001 | US6285605 Integrated memory having redundant units of memory cells, and test method for the redundant units |
| 09/04/2001 | US6285604 Dummy memory cells for high accuracy self-timing circuits in dual-port SRAM |
| 09/04/2001 | US6285603 Repair circuit of semiconductor memory device |
| 09/04/2001 | US6285602 Semiconductor memory device provided with I/O clamp circuit |
| 09/04/2001 | US6285601 Method and apparatus for multi-level buffer thresholds for higher efficiency data transfers |
| 09/04/2001 | US6285590 Low power consumption semiconductor ROM, EPROM, EEPROM and like circuit |
| 09/04/2001 | US6285585 Output switching implementation for a flash memory device |
| 09/04/2001 | US6285574 Symmetric segmented memory array architecture |
| 09/04/2001 | US6285573 Semiconductor integrated circuit having shield wire |
| 09/04/2001 | US6285217 Dynamic logic circuits with reduced evaluation time |
| 09/04/2001 | US6285216 High speed output enable path and method for an integrated circuit device |
| 09/04/2001 | US6284585 Electronic memory device having bit lines with block selector switches |
| 08/30/2001 | WO2001063442A1 Sound and image producing system |
| 08/30/2001 | US20010018750 Method for powering down unused configuration bits to minimize power consumption |
| 08/30/2001 | US20010018726 Memory refreshing system |
| 08/30/2001 | US20010018725 Controlling reading from and writing to a semiconductor memory device |
| 08/30/2001 | US20010017810 Semiconductor memory device |
| 08/30/2001 | US20010017809 Circuit configuration having a variable number of data outputs and device for reading out data from the circuit configuration with the variable number of data outputs |
| 08/30/2001 | US20010017807 Semiconductor memory device allowing static-charge tolerance test between bit lines |
| 08/30/2001 | US20010017805 Automatic precharge apparatus of semiconductor memory device |
| 08/30/2001 | US20010017803 Semiconductor memory |
| 08/30/2001 | US20010017801 Method and data processing system for data lookups |
| 08/30/2001 | US20010017796 Semiconductor memory device for distributing load of input and output lines |
| 08/30/2001 | US20010017793 PLD with on-chip memory having a shadow |
| 08/30/2001 | US20010017792 Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other |
| 08/30/2001 | US20010017790 Synchronous semiconductor memeory device and method for reading data |
| 08/30/2001 | US20010017787 Semiconductor memory device |
| 08/30/2001 | US20010017368 Semiconductor memory devices and methods for sampling data therefrom based on a relative position of a memory cell array section containing the data |
| 08/29/2001 | EP1127306A1 A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state |
| 08/29/2001 | EP0830682B1 Auto-activate on synchronous dynamic random access memory |
| 08/29/2001 | CN1310532A Data transmission method and system |
| 08/29/2001 | CN1310451A Recording medium, recording equipment and recording/reproducing system |
| 08/29/2001 | CN1310450A Apparatus and method for processing data |
| 08/28/2001 | US6282603 Memory with pipelined accessed and priority precharge |
| 08/28/2001 | US6282456 Digital audio processor |
| 08/28/2001 | US6282210 Clock driver with instantaneously selectable phase and method for use in data communication systems |
| 08/28/2001 | US6282150 Semiconductor memory device |
| 08/28/2001 | US6282142 Semiconductor memory device |
| 08/28/2001 | US6282141 Semiconductor memory device and memory system |
| 08/28/2001 | US6282138 Latched sense amplifier with tri-state outputs |
| 08/28/2001 | US6282137 SRAM method and apparatus |
| 08/28/2001 | US6282136 Semiconductor memory devices and sensors using the same |
| 08/28/2001 | US6282135 Intializing memory cells within a dynamic memory array prior to performing internal memory operations |
| 08/28/2001 | US6282133 Semiconductor memory device having a delay circuit for generating a read timing |
| 08/28/2001 | US6282132 Data-strobe input buffers for high-frequency SDRAMS |
| 08/28/2001 | US6282131 Self-timed clock circuitry in a multi-bank memory instance using a common timing synchronization node |
| 08/28/2001 | US6282129 Memory devices and memory reading methods |
| 08/28/2001 | US6282128 Integrated circuit memory devices having multiple data rate mode capability and methods of operating same |
| 08/28/2001 | US6282127 Block RAM with reset to user selected value |
| 08/28/2001 | US6282117 Nonvolatile semiconductor memory device |
| 08/28/2001 | US6282114 Low consumption ROM |
| 08/28/2001 | US6282113 Four F-squared gapless dual layer bitline DRAM array architecture |
| 08/28/2001 | US6281728 Delay locked loop circuit |
| 08/28/2001 | US6281726 Device and method in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution |
| 08/28/2001 | US6281714 Differential receiver |
| 08/28/2001 | US6281713 Current sense amplifiers having equalization circuits therin that inhibit signal oscillations during active modes |
| 08/28/2001 | US6281519 Quantum semiconductor memory device including quantum dots |
| 08/23/2001 | WO2001061705A1 Memory device with support for unaligned access |
| 08/23/2001 | WO2001061704A1 Audio playback device |
| 08/23/2001 | WO2001061692A1 A portable data storage device |
| 08/23/2001 | US20010016893 Layout for a semiconductor memory device having redundant elements |
| 08/23/2001 | US20010016022 Delay time adjusting circuit comprising frequency dividers having different frequency division rates |