| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 07/10/2001 | US6260097 Method and apparatus for controlling a synchronous memory device |
| 07/10/2001 | US6259652 Synchronous integrated memory |
| 07/10/2001 | US6259650 Dual port memory control signals with synchronized read and write pointers |
| 07/10/2001 | US6259647 Synchronous semiconductor memory device allowing easy and fast test |
| 07/10/2001 | US6259646 Fast accessing of a memory device |
| 07/10/2001 | US6259645 Matching loading between sensing reference and memory cell with reduced transistor count in a dual-bank flash memory |
| 07/10/2001 | US6259642 Semiconductor memory device with reduced sensing noise and sensing current |
| 07/10/2001 | US6259641 Integrated memory having sense amplifiers disposed on opposite sides of a cell array |
| 07/10/2001 | US6259637 Method and apparatus for built-in self-repair of memory storage arrays |
| 07/10/2001 | US6259636 Semiconductor memory device having redundancy circuit for relieving faulty memory cells |
| 07/10/2001 | US6259634 Pseudo dual-port DRAM for simultaneous read/write access |
| 07/10/2001 | US6259633 Sense amplifier architecture for sliding banks for a simultaneous operation flash memory device |
| 07/10/2001 | US6259628 Memory devices with verifying input/output buffer circuits and methods of operation thereof |
| 07/10/2001 | US6259622 Two bit per cell ROM using a two phase current sense amplifier |
| 07/10/2001 | US6259621 Method and apparatus for minimization of data line coupling in a semiconductor memory device |
| 07/10/2001 | US6259288 Semiconductor integrated circuit having a DLL circuit and a special power supply circuit for the DLL circuit |
| 07/10/2001 | US6259018 Conductor structure |
| 07/05/2001 | US20010007141 Circuit and method for masking a dormant memory cell |
| 07/05/2001 | US20010007136 Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
| 07/05/2001 | US20010007115 Output drivers preventing degradation of channel bus line in a memory module equipped with semiconductor memory devices including the output drivers |
| 07/05/2001 | US20010006483 Fast cycle RAM and data readout method therefor |
| 07/05/2001 | US20010006479 Read circuit of nonvolatile semiconductor memory |
| 07/05/2001 | US20010006476 Static memory cell having independent data holding voltage |
| 07/05/2001 | US20010006247 Semiconductor memory device with a triple well structure |
| 07/05/2001 | DE19964064A1 Medium for a media player for recording and playing media on CD and DVD has a cassette medium as a traditional music compact cassette with an energy supply unit to adapt a driving mechanism in a media player. |
| 07/05/2001 | DE19961518A1 Verfahren zum Betreiben eines Strom-Leseverstärkers A method of operating a current sense amplifier |
| 07/05/2001 | DE10065703A1 Column-transistor in semiconductor device, such as a memory device, has gate electrode of column transistor bent in the active zone of the column transistor so as to increase the width of the transistor |
| 07/05/2001 | DE10061805A1 Flashspeicher mit Burstmodus Flash memory with burst mode |
| 07/04/2001 | EP1113448A1 Circuit for an integrated semiconductor memory with row access |
| 07/04/2001 | EP1113447A1 Information storage apparatus and information processing method using the same and connector pin assembly |
| 07/04/2001 | EP1113446A1 Data reproduction device |
| 07/04/2001 | EP1113438A2 Medium for media player |
| 07/04/2001 | EP1078370A4 Sense amplifier with zero power idle mode |
| 07/04/2001 | CN1302428A Recording device, recording method, reproducing device and reproducing method |
| 07/04/2001 | CN1302404A Data processing device, data processing method, terminal, transmission method for data processing device |
| 07/04/2001 | CN1302085A Rowed transistor in semiconductor |
| 07/03/2001 | US6256754 Memory system having internal state monitoring circuit |
| 07/03/2001 | US6256703 Adaptive memory control |
| 07/03/2001 | US6256681 Data buffer for programmable memory |
| 07/03/2001 | US6256604 Memory integrated with logic on a semiconductor chip and method of designing the same |
| 07/03/2001 | US6256262 High speed memory device having different read and write clock signals |
| 07/03/2001 | US6256261 Memory device with packet command |
| 07/03/2001 | US6256260 Synchronous semiconductor memory device having input buffers and latch circuits |
| 07/03/2001 | US6256259 Delay-locked loop with binary-coupled capacitor |
| 07/03/2001 | US6256258 Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory |
| 07/03/2001 | US6256256 Dual port random access memories and systems using the same |
| 07/03/2001 | US6256255 Multi-bank memory input/output line selection |
| 07/03/2001 | US6256253 Memory device with support for unaligned access |
| 07/03/2001 | US6256252 Memory-embedded semiconductor integrated circuit device having low power consumption |
| 07/03/2001 | US6256248 Method and apparatus for increasing the time available for internal refresh for 1-T SRAM compatible devices |
| 07/03/2001 | US6256246 Semiconductor memory device |
| 07/03/2001 | US6256245 Precharging apparatus and method in a semiconductor memory device |
| 07/03/2001 | US6256236 Semiconductor device capable of implementing simultaneous signal input and output from and to the same external terminal |
| 07/03/2001 | US6256235 Adjustable driver pre-equalization for memory subsystems |
| 07/03/2001 | US6256234 Low skew differential receiver with disable feature |
| 07/03/2001 | US6256233 Distributed signal drivers in arrayable devices |
| 07/03/2001 | US6256221 Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines |
| 07/03/2001 | US6256219 Integrated memory having memory cells disposed at crossover points of word lines and bit lines |
| 07/03/2001 | US6256218 Integrated circuit memory devices having adjacent input/output buffers and shift blocks |
| 07/03/2001 | US6255862 Latch type sense amplifier circuit |
| 06/28/2001 | WO2001046959A1 A multi-level, low voltage swing sensing scheme for high speed memory design |
| 06/28/2001 | US20010005878 Data reproduction device |
| 06/28/2001 | US20010005828 Audio playback/recording apparatus |
| 06/28/2001 | US20010005373 Virtual channel DRAM |
| 06/28/2001 | US20010005337 Delay locked loop having fast locking time |
| 06/28/2001 | US20010005336 Semiconductor memory having an overlaid bus structure |
| 06/28/2001 | US20010005334 Semiconductor memory device |
| 06/28/2001 | US20010005331 Dual-to -single-rail converter for the read out of static storage arrays |
| 06/28/2001 | US20010005325 Semiconductor memory device |
| 06/28/2001 | US20010005291 Information storage apparatus and information processing apparatus using the same |
| 06/28/2001 | US20010005157 Semiconductor device using complementary clock and signal input state detection circuit used for the same |
| 06/28/2001 | US20010005150 Latch type sense amplifier and method for operating thereof |
| 06/28/2001 | US20010005049 Memory device with multiple input/output connections |
| 06/28/2001 | US20010005012 Fast cycle ram having improved data write operation |
| 06/28/2001 | DE10053507A1 Semiconductor memory e.g. SRAM, has sense amp circuit with positive feedback circuit having differential pairs of P-channel type field effect transistors and gates of transistors in each pair are connected mutually |
| 06/27/2001 | EP1111782A2 Differential sense amplifier circuit and dynamic logic circuit using the same |
| 06/27/2001 | EP1111618A1 Read/write protected electrical fuse architecture |
| 06/27/2001 | EP1111617A2 Method and apparatus for processing data |
| 06/27/2001 | EP1111616A2 Recording medium and information processing device for managing read-in information |
| 06/27/2001 | EP1111615A1 Logic circuit |
| 06/27/2001 | CN1301024A Differential reading-out amplifying circuit and dynamic logic circuit for using it |
| 06/27/2001 | CN1301023A Logic circuit |
| 06/26/2001 | US6253298 Synchronous SRAM having pipelined enable |
| 06/26/2001 | US6253278 Synchronous DRAM modules including multiple clock out signals for increasing processing speed |
| 06/26/2001 | US6252820 Semiconductor memory device capable of monitoring and adjusting the timing and pulse width of internal control signals |
| 06/26/2001 | US6252815 First in first out memory circuit |
| 06/26/2001 | US6252814 Dummy wordline circuitry |
| 06/26/2001 | US6252812 Semiconductor memory device utilizing multiple edges of a signal |
| 06/26/2001 | US6252804 Semiconductor integrated circuit, and method of controlling same |
| 06/26/2001 | US6252794 DRAM and data access method for DRAM |
| 06/26/2001 | US6252791 Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems |
| 06/26/2001 | US6252788 Semiconductor integrated circuit device |
| 06/26/2001 | US6252462 Capacitor transimpedance amplifier ( CTIA) with shared load |
| 06/26/2001 | US6252441 Synchronous data sampling circuit |
| 06/26/2001 | US6252431 Shared PMOS sense amplifier |
| 06/26/2001 | US6252429 Method and apparatus for improving device matching and switching point tolerance in silicon-on-insulator cross-coupled circuits |
| 06/26/2001 | US6252263 Layout structure for dynamic random access memory |
| 06/21/2001 | WO2001045112A1 Mobile communication device having flash memory system with word line buffer |
| 06/21/2001 | WO2001045110A1 Data storage device and corresponding method |
| 06/21/2001 | WO2001045106A2 Mobile communication device having integrated embedded flash and sram memory |