G11C 7 - Arrangements for writing information into, or reading information out from, a digital store

Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
11/2004
11/16/2004	US6819616 Serial to parallel data input methods and related input buffers
11/16/2004	US6819615 Memory device having resistive element coupled to reference cell for improved reliability
11/16/2004	US6819614 Semiconductor memory device and sensing control method having more stable input/output line sensing control
11/16/2004	US6819613 Semiconductor device
11/16/2004	US6819612 Apparatus and method for a sense amplifier circuit that samples and holds a reference voltage
11/16/2004	US6819610 DRAM operating like SRAM
11/16/2004	US6819603 Method of controlling a delay locked loop
11/16/2004	US6819602 Multimode data buffer and method for controlling propagation delay time
11/16/2004	US6819600 Semiconductor memory device with offset-compensated sensing scheme
11/16/2004	US6819599 Programmable DQS preamble
11/16/2004	US6819581 Ferroelectric nonvolatile semiconductor memory
11/16/2004	US6819151 Method and circuit for adjusting the timing of output data based on an operational mode of output drivers
11/16/2004	US6819144 Latched sense amplifier with full range differential input voltage
11/16/2004	US6819133 System and method for protecting configuration data for a programmable execution unit
11/16/2004	CA2186139C An improved cost/performance system memory unit using extended data out dynamic random access memory
11/11/2004	WO2004097841A1 Flash memory having a spare sector of reduced access time
11/11/2004	WO2004097835A2 Nonvolatile memory structure with high speed high bandwidth and low voltage
11/11/2004	WO2004097727A1 Memory card
11/11/2004	WO2004034440A3 Current integrating sense amplifier for memory modules in rfid
11/11/2004	US20040225946 Method and circuit for error correction, error correction encoding, data reproduction, or data recording
11/11/2004	US20040225945 Concept for a secure data communication between electronic devices
11/11/2004	US20040225944 Systems and methods for processing an error correction code word for storage in memory components
11/11/2004	US20040225852 Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM
11/11/2004	US20040225828 Storage and reproduction apparatus
11/11/2004	US20040225827 Apparatus and method for determining erasability of data
11/11/2004	US20040225825 Scratch control memory array in a flash memory device
11/11/2004	US20040223610 Apparatus and method for performing transparent cipher block chaining mode cryptographic functions
11/11/2004	US20040223571 Delay locked loop circuitry for clock delay adjustment
11/11/2004	US20040223437 Optical disc playback apparatus and method for detecting mirror surface of optical disc
11/11/2004	US20040223402 Nonvolatile ferroelectric memory and control device using the same
11/11/2004	US20040223401 Semiconductor integrated-circuit device and method to speed-up CMOS circuit
11/11/2004	US20040223395 Hiding error detecting/correcting latency in dynamic random access memory (DRAM)
11/11/2004	US20040223394 Position based erase verification levels in a flash memory device
11/11/2004	US20040223393 Skewed sense AMP for variable resistance memory sensing
11/11/2004	US20040223392 Semiconductor memory device
11/11/2004	US20040223391 Integrated realization of sensing and processing
11/11/2004	US20040223388 Data write circuit
11/11/2004	US20040223376 Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier
11/11/2004	US20040223374 Synchronous up/down address generator for burst mode read
11/11/2004	US20040223367 Phase detector for all-digital phase locked and delay locked loops
11/11/2004	US20040223365 Semiconductor device and method for inputting/outputting data simultaneously through single pad
11/11/2004	US20040223360 Semiconductor memory device
11/11/2004	US20040223354 Semiconductor memory device having high-speed input/output architecture
11/11/2004	US20040222828 Timing adjustment circuit and semiconductor device including the same
11/11/2004	US20040222820 Driver circuit having a plurality of drivers for driving signals in parallel
11/11/2004	US20040222450 MRAM architecture with a bit line located underneath the magnetic tunneling junction device
11/11/2004	DE10315528A1 Data memory circuit for drams has memory cells command decoder control unit and a command buffer to store commands during inadmissible command events
11/11/2004	DE102004006456A1 Integrierte Schaltung und zugehöriges Schnittstellenverfahren Integrated circuit and associated interface method
11/10/2004	EP1475805A2 Semiconductor memory device
11/10/2004	EP1475718A2 A semiconductor memory device
11/10/2004	EP1475717A2 A data processing structure unit
11/10/2004	EP1475716A2 A data processing unit, a data processing structure unit, and a data processing structure
11/10/2004	EP1474805A2 Methods and apparatus for adaptively adjusting a data receiver
11/10/2004	EP1474804A2 Reading circuit for reading a memory cell
11/10/2004	EP1474749A2 Method and apparatus for supplementary command bus in a computer system
11/10/2004	CN1545708A Method and device for testing semiconductor memory devices
11/10/2004	CN1175421C Logic circuit
11/09/2004	USRE38647 Sense amplifier circuit
11/09/2004	US6817003 Short edge management in rule based OPC
11/09/2004	US6816991 Built-in self-testing for double data rate input/output
11/09/2004	US6816433 Synchronous dynamic random access memory for burst read/write operations
11/09/2004	US6816431 Magnetic random access memory using memory cells with rotated magnetic storage elements
11/09/2004	US6816426 Semiconductor device with self refresh test mode
11/09/2004	US6816425 Balanced sense amplifier control for open digit line architecture memory devices
11/09/2004	US6816423 System for control of pre-charge levels in a memory device
11/09/2004	US6816421 Nonvolatile semiconductor memory
11/09/2004	US6816420 Column redundancy scheme for serially programmable integrated circuits
11/09/2004	US6816418 MIS semiconductor device having improved gate insulating film reliability
11/09/2004	US6816417 Input/output buffer circuit
11/09/2004	US6816416 Memory device having reduced layout area
11/09/2004	US6816410 Method for programming a three-dimensional memory array incorporating serial chain diode stack
11/09/2004	US6816403 Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices
11/09/2004	US6816397 Bi-directional read write data structure and method for memory
11/09/2004	US6816094 Circuit configuration for the bit-parallel outputting of a data word
11/09/2004	US6815990 Delay locked loops having blocking circuits therein that enhance phase jitter immunity and methods of operating same
11/09/2004	US6815982 Electrical or electronic circuit arrangement and associated method
11/09/2004	US6815811 Semiconductor integrated circuit with dummy patterns
11/09/2004	US6815804 High permeability composite films to reduce noise in high speed interconnects
11/09/2004	US6815742 System with meshed power and signal buses on cell array
11/04/2004	WO2004095471A1 Semiconductor memory
11/04/2004	WO2004095467A1 Semiconductor memory
11/04/2004	WO2004095466A1 Semiconductor memory
11/04/2004	WO2004095465A1 Semiconductor memory
11/04/2004	WO2004095463A1 Method for reducing power consumption when sensing a resistive memory
11/04/2004	WO2004095461A2 Redundant memory structure using bad bit pointers
11/04/2004	WO2004095460A2 Asynchronous jitter reduction technique
11/04/2004	US20040221129 Semiconductor memory device having tag block for reducing initialization time
11/04/2004	US20040221119 Input/output data pipeline circuit of semiconductor memory device and the semiconductor memory device
11/04/2004	US20040221098 Semiconductor integrated circuit device
11/04/2004	US20040221097 Destructive-read random access memory system buffered with destructive-read memory cache
11/04/2004	US20040219745 Memory device for reducing skew of data and address
11/04/2004	US20040219729 Flash memory device
11/04/2004	US20040218461 Semiconductor device for domain crossing
11/04/2004	US20040218460 Synchronous memory device for preventing erroneous operation due to DQS ripple
11/04/2004	US20040218457 Memory architecture with single-port cell and dual-port (read and write) functionality
11/04/2004	US20040218456 Semiconductor memory device
11/04/2004	US20040218454 Method and apparatus for implementing dram redundancy fuse latches using sram
11/04/2004	US20040218447 Method for sensing bit line with uniform sensing margin time and memory device thereof
11/04/2004	US20040218446 Sense amplifier configuration for a semiconductor memory device
11/04/2004	US20040218443 Hybrid semiconductor-magnetic device and method of operation

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