Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
01/2005
01/13/2005WO2005004164A1 Semiconductor storage device
01/13/2005WO2005004138A1 Recording medium, method of configuring control information thereof, recording and/or reproducing method using the same, and apparatus thereof
01/13/2005WO2004075257A3 Memory having variable refresh control and method therefor
01/13/2005US20050010841 Memory module and method of testing the same
01/13/2005US20050010834 Method and apparatus for determining the write delay time of a memory
01/13/2005US20050010833 Apparatus and methods for improved input/output cells
01/13/2005US20050010741 Memory system and timing control method of the same
01/13/2005US20050010714 Schmoo runtime reduction and dynamic calibration based on a DLL lock value
01/13/2005US20050010713 Scheme for optimal settings for DDR interface
01/13/2005US20050008344 Digital system for recording video signals
01/13/2005US20050007916 Recording medium, method of configuring control information thereof, recording and/or reproducing method using the same, and apparatus thereof
01/13/2005US20050007863 Sampling frequency conversion device and sampling frequency conversion method
01/13/2005US20050007862 Semiconductor device having mechanism capable of high-speed operation
01/13/2005US20050007853 Recording medium, method of configuring control information thereof, recording and/or reproducing method using the same, and apparatus thereof
01/13/2005US20050007851 Semiconductor storage device
01/13/2005US20050007850 Noise resistant small signal sensing circuit for a memory device
01/13/2005US20050007849 DRAM memory circuit with sense amplifiers
01/13/2005US20050007848 Method and system for using dynamic random access memory as cache memory
01/13/2005US20050007846 Semiconductor integrated circuit device
01/13/2005US20050007843 Redundancy circuit in semiconductor memory device having a multiblock structure
01/13/2005US20050007842 Amplifying circuit, amplifying apparatus, and memory apparatus
01/13/2005US20050007837 Clock generator for pseudo dual port memory
01/13/2005US20050007836 Data strobe synchronization circuit and method for double data rate, multi-bit writes
01/13/2005US20050007835 Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods
01/13/2005US20050007833 Memory cell strings
01/13/2005US20050007830 System and method for reading a memory cell
01/13/2005US20050007825 Memory cell strings in a resistive cross point memory cell array
01/13/2005US20050007818 Thin film magnetic memory device including memory cells having a magnetic tunnel junction
01/13/2005US20050007817 High permeability composite films to reduce noise in high speed interconnects
01/13/2005US20050007814 Multiple buffer memory interface
01/13/2005US20050007813 Lower power and reduced device split local and continuous bitline for domino read SRAMs
01/13/2005US20050007804 Structure and method of multiplexing bitline signals within a memory array
01/13/2005US20050007803 Noise resistant small signal sensing circuit for a memory device
01/13/2005US20050007170 Asynchronous control circuit and semiconductor integrated circuit device
01/13/2005US20050007156 Sense amplifier and electronic apparatus using the same
01/13/2005US20050007146 Reducing coupling noise in an output driver
01/13/2005US20050006727 High permeability composite films to reduce noise in high speed interconnects
01/13/2005DE10392198T5 Erhöhen einer Auffrischperiode (Refresh Period) in einer Halbleiterspeichervorrichtung Increasing a refresh (refresh period) in a semiconductor memory device
01/13/2005DE10361678A1 Voraufladegerät in einer Halbleiterspeichervorrichtung und Voraufladeverfahren unter Verwendung desselben Voraufladegerät thereof in a semiconductor memory device, and pre-charging using
01/13/2005DE10339665B3 Semiconductor memory device operating method, by leaving active the cells in sub-array if access is to be made to further memory cells in same memory cell array
01/13/2005DE102004027882A1 Multi-port memory device for video camera, has data line sense amplifiers sensing data read from memory cells of selected banks, and read data lines simultaneously transmitting data from amplifiers to buffers
01/13/2005DE102004026526A1 Integrated circuit memory device e.g. fast cycle dynamic RAM, for use in e.g. consumer application, has write data path with N data lines connecting N switches to memory cell array to write N data bits in parallel
01/12/2005EP1496697A1 Digital system for recording video signals
01/12/2005EP1496519A2 Encoding method and memory apparatus
01/12/2005EP1496518A1 Storage device using resistance varying storage element and reference resistance value decision method for the device
01/12/2005EP1496421A2 Apparatus and method for performing transparent block cipher cryptographic functions
01/12/2005EP1495471A1 System and method for generating a reference voltage based on averaging the voltages of two complementary programmed dual bit reference cells
01/12/2005EP1295294B1 Burst architecture for a flash memory
01/12/2005EP1208567B1 Double data rate scheme for data output
01/12/2005CN1565034A Synchronous semiconductor storage device module and its control method, information device
01/12/2005CN1564261A MP3 playback device having multi-file synchronous playing function and its method
01/12/2005CN1564260A Magnetic DASD based on vertical current writing and its control method
01/12/2005CN1184525C Optical logic element and methods for respectively its preparation and optical adressing, as well as the use thereof in optical logic device
01/11/2005USRE38685 Data-output driver circuit and method
01/11/2005US6842864 Method and apparatus for configuring access times of memory devices
01/11/2005US6842815 Output drivers preventing degradation of channel bus line in a memory module equipped with semiconductor memory devices including the output drivers
01/11/2005US6842405 Automatic selection of recording mode in portable digital audio recorder
01/11/2005US6842398 Multi-mode synchronous memory device and methods of operating and testing same
01/11/2005US6842397 Clock-synchronous semiconductor memory device
01/11/2005US6842396 Semiconductor memory device with clock generating circuit
01/11/2005US6842395 Semiconductor memory card, method of controlling the same and interface apparatus for semiconductor memory card
01/11/2005US6842391 Semiconductor memory of a dynamic random access memory (DRAM) type having a static random access memory (SRAM) interface
01/11/2005US6842388 Semiconductor memory device with bit line precharge voltage generating circuit
01/11/2005US6842386 Semiconductor integrated circuit, and a data storing method thereof
01/11/2005US6842385 Automatic reference voltage regulation in a memory device
01/11/2005US6842384 Nonvolatile semiconductor memory with power-up read mode
01/11/2005US6842377 Nonvolatile semiconductor memory device with first and second read modes
01/11/2005US6842373 Command decoder and decoding method for use in semiconductor memory device
01/11/2005US6842364 Memory cell strings in a resistive cross point memory cell array
01/11/2005US6842065 Electrical fuse programming control circuit
01/11/2005US6841821 Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
01/07/2005WO2005004134A1 A recording medium, method of configuring control information thereof, method for recording or reproducing data using the same, and apparatus thereof
01/06/2005WO2005002052A2 Bi-directional buffering for memory data lines
01/06/2005WO2005001899A2 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
01/06/2005WO2005001839A2 High performance gain cell architecture
01/06/2005WO2005001694A1 Data transfer method and system
01/06/2005WO2004051490A3 Memory system comprising a plurality of memory controllers and method for synchronizing the same
01/06/2005US20050005230 Semiconductor integrated circuit device and error checking and correcting method thereof
01/06/2005US20050005184 Method for measuring and compensating skews of data transmission lines
01/06/2005US20050005183 Fast data access mode in a memory device
01/06/2005US20050005179 Method and apparatus for calibrating a multi-level current mode driver
01/06/2005US20050005069 Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration
01/06/2005US20050005056 Method and apparatus for controlling a read valid window of a synchronous memory device
01/06/2005US20050005054 Memory system having data inversion and data inversion method for a memory system
01/06/2005US20050005053 Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion
01/06/2005US20050003610 Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices
01/06/2005US20050003603 Semiconductor storage device
01/06/2005US20050002264 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
01/06/2005US20050002261 Semiconductor memory device with a bypass circuit for verifying the characteristics of an internal clock signal
01/06/2005US20050002260 Light emitting device and electronic equipment
01/06/2005US20050002259 Semiconductor storage device
01/06/2005US20050002258 Semiconductor storage device, method for protecting predetermined memory element and portable electronic equipment
01/06/2005US20050002252 Semiconductor memory device and current mirror circuit
01/06/2005US20050002251 Semiconductor device
01/06/2005US20050002250 Method and apparatus for amplifying a regulated differential signal to a higher voltage
01/06/2005US20050002249 Method and apparatus for measuring current as in sensing a memory cell
01/06/2005US20050002247 Shared sense amplifier scheme semiconductor memory device and method of testing the same
01/06/2005US20050002246 Memory module with integrated bus termination
01/06/2005US20050002245 Method and apparatus for optimizing the functioning of DRAM memory elements
01/06/2005US20050002244 Semiconductor storage device, redundancy circuit thereof, and portable electronic device