| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
|---|
| 08/10/2004 | US6775185 Nonvolatile semiconductor memory |
| 08/10/2004 | US6775177 Semiconductor memory device switchable to twin memory cell configuration |
| 08/10/2004 | US6775174 Memory architecture for micromirror cell |
| 08/10/2004 | US6775170 Semiconductor memory device having write column select line or read column select line for shielding signal line |
| 08/10/2004 | US6775165 Current switching sensor detector |
| 08/10/2004 | US6774892 Display driver IC |
| 08/10/2004 | US6774734 Ring oscillator circuit for EDRAM/DRAM performance monitoring |
| 08/10/2004 | US6774693 Digital delay line with synchronous control |
| 08/10/2004 | US6774690 Digital dual-loop DLL design using coarse and fine loops |
| 08/10/2004 | US6774677 Device for linking a processor to a memory element and memory element |
| 08/10/2004 | US6774444 Forming p-type well region by epitaxial growth; doping; forming barrier and photosensor layers |
| 08/10/2004 | US6773986 Method for fabricating a semiconductor memory device |
| 08/10/2004 | US6773983 Memory cell arrangement and method for its fabrication |
| 08/10/2004 | CA2429250C Portable electronic device having a log-structured file system in flash memory |
| 08/05/2004 | WO2004027589A3 Clock distribution topology |
| 08/05/2004 | WO2003069461A3 Methods and apparatus for adaptively adjusting a data receiver |
| 08/05/2004 | US20040153976 High speed low power bitline |
| 08/05/2004 | US20040153632 Method and software for partitioned group element selection operation |
| 08/05/2004 | US20040153613 Burst write in a non-volatile memory device |
| 08/05/2004 | US20040153602 Detection circuit for mixed asynchronous and synchronous memory operation |
| 08/05/2004 | US20040153599 Data compression read mode for memory testing |
| 08/05/2004 | US20040152279 Semiconductor latches and SRAM devices |
| 08/05/2004 | US20040151054 Selectable clock input |
| 08/05/2004 | US20040151053 Double data rate memory interface |
| 08/05/2004 | US20040151052 Semiconductor memory device with magnetic disturbance reduced |
| 08/05/2004 | US20040151048 Semiconductor memory device capable of reading data of signature fuse through normal read operation and method of reading data of signature fuse in semiconductor memory device through normal read operation |
| 08/05/2004 | US20040151046 Sense amplifier with adaptive reference generation |
| 08/05/2004 | US20040151045 Non-volatile memory device |
| 08/05/2004 | US20040151044 Methods and circuits for balancing bitline precharge |
| 08/05/2004 | US20040151042 Methods and systems for reducing heat flux in memory systems |
| 08/05/2004 | US20040151041 Dual port semiconductor memory device |
| 08/05/2004 | US20040151040 Composite storage apparatus and a card board thereof |
| 08/05/2004 | US20040151038 Memory module and method for operating a memory module in a data memory system |
| 08/05/2004 | US20040151036 Magnetic head for performing perpendicular magnetic recording in a disk drive |
| 08/05/2004 | US20040151035 Method and device for timing random reading of a memory device |
| 08/05/2004 | US20040151033 Semiconductor integrated circuit and IC card |
| 08/05/2004 | US20040151032 High speed and low noise output buffer |
| 08/05/2004 | US20040151030 Method of narrowing threshold voltage distribution |
| 08/05/2004 | US20040151026 Chip protection register unlocking |
| 08/05/2004 | US20040151023 Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices |
| 08/05/2004 | US20040151022 Memory trouble relief circuit |
| 08/05/2004 | US20040151015 Read only memory device |
| 08/05/2004 | US20040151013 Semiconductor memory |
| 08/05/2004 | US20040150735 Layout technique for address signal lines in decoders including stitched blocks |
| 08/05/2004 | US20040150470 SOI sense amplifier method and apparatus |
| 08/05/2004 | US20040150465 Interpolating sense amplifier circuits and methods of operating the same |
| 08/05/2004 | US20040150440 Clock synchronization circuit and semiconductor device |
| 08/05/2004 | US20040150435 Method and apparatus for regulating predriver for output buffer |
| 08/05/2004 | US20040150018 Semiconductor device having sense amplifier including paired transistors |
| 08/05/2004 | DE10334424A1 Halbleiterspeichervorrichtung mit Doppelzelleneinheiten A semiconductor memory device with dual cell units |
| 08/05/2004 | DE10322882A1 Integrated memory circuit with dynamic memory cell, into which date is to be written, fitted on word line and bit line, while read-out amplifier is coupled to two supply lines for high and low supply potential respectively to amplify charge |
| 08/05/2004 | DE10302224A1 Integrierter Speicher Built-in Memory |
| 08/05/2004 | DE10255867B3 Dynamischer RAM-Halbleiterspeicher und Verfahren zum Betrieb desselben A dynamic random access semiconductor memory and method of operation thereof |
| 08/04/2004 | EP1443760A1 Data processing unit and method, and program |
| 08/04/2004 | EP1443412A2 Information processing apparatus and memory access arranging method |
| 08/04/2004 | EP1442462A1 Using transfer bits during data transfer from non-volatile to volatile memories |
| 08/04/2004 | EP1442454A2 Digital audio device |
| 08/04/2004 | CN1518742A Low power hynamic RAM with bit line pre-charge, inversion data write and storing data output |
| 08/04/2004 | CN1518033A Electronic device with wide lens and for small firing point size |
| 08/04/2004 | CN1517997A Semiconductor storing device with double-unit |
| 08/04/2004 | CN1517995A Current refrence generator for magnetic RAM |
| 08/04/2004 | CN1517687A Temp. checking circuit unsensing for change of supply voltage and temp |
| 08/04/2004 | CN1160735C Input receiver circuit |
| 08/04/2004 | CN1160629C Device, method and system for read/write data |
| 08/03/2004 | US6772359 Clock control circuit for Rambus DRAM |
| 08/03/2004 | US6772351 Method and apparatus for calibrating a multi-level current mode driver |
| 08/03/2004 | US6772312 Semiconductor memory having asynchronous pipeline stages |
| 08/03/2004 | US6772278 Data transfer system and data transfer method |
| 08/03/2004 | US6772277 Method of writing to a memory array using clear enable and column clear signals |
| 08/03/2004 | US6772273 Block-level read while write method and apparatus |
| 08/03/2004 | US6771887 Recording/reproducing apparatus and recording/reproducing method |
| 08/03/2004 | US6771558 Semiconductor memory device |
| 08/03/2004 | US6771557 Predecode column architecture and method |
| 08/03/2004 | US6771552 Semiconductor memory device and control method |
| 08/03/2004 | US6771551 Sense amplifier with adaptive reference generation |
| 08/03/2004 | US6771550 Semiconductor memory device with stable precharge voltage level of data lines |
| 08/03/2004 | US6771549 Row-column repair technique for semiconductor memory arrays |
| 08/03/2004 | US6771543 Precharging scheme for reading a memory cell |
| 08/03/2004 | US6771530 Semiconductor memory and method for driving the same |
| 08/03/2004 | US6771529 ROM embedded DRAM with bias sensing |
| 08/03/2004 | US6771108 Input circuit and semiconductor integrated circuit having the input circuit |
| 08/03/2004 | US6769603 Data recording and reproducing apparatus and data reproducing apparatus |
| 07/29/2004 | WO2004063906A2 Coded write masking |
| 07/29/2004 | WO2004063756A1 Method and apparatus for detecting an unused state in a semiconductor circuit |
| 07/29/2004 | WO2004044757A3 Method and apparatus for data acquisition |
| 07/29/2004 | WO2003107349A3 Methods and apparatus for delay circuit |
| 07/29/2004 | US20040148557 Data storing method of dynamic RAM and semiconductor memory device |
| 07/29/2004 | US20040148538 Method and apparatus for providing symmetrical output data for a double data rate DRAM |
| 07/29/2004 | US20040148457 Semiconductor memory device |
| 07/29/2004 | US20040145963 Semiconductor device including duty cycle correction circuit |
| 07/29/2004 | US20040145962 Circuit for generating a data strobe signal used in a double data rate synchronous semiconductor device |
| 07/29/2004 | US20040145959 Semiconductor memory device with reduced current consumption during standby state |
| 07/29/2004 | US20040145423 Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals |
| 07/29/2004 | US20040145408 Semiconductor device having logic circuit and macro circuit |
| 07/29/2004 | US20040145404 Pre-biased voltage level shifting circuit for integrated circuit devices utilizing differing power supply levels |
| 07/29/2004 | US20040144994 Apparatus and methods for optically-coupled memory systems |
| 07/29/2004 | US20040144978 Organic light emitting device with constant luminance |
| 07/29/2004 | DE102004002437A1 Verzögerungsregelkreis, integrierte Schaltung und Betriebsverfahren Delay locked loop, integrated circuit and method of operation |
| 07/28/2004 | EP1441359A1 Memory system for a multibus architecture |
| 07/28/2004 | EP1440446A1 Non-volatile memory with temperature-compensated data read |