Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
10/2004
10/14/2004US20040205428 Redundancy circuit and semiconductor device using the same
10/14/2004US20040205426 Method of deciding error rate and semiconductor integrated circuit device
10/14/2004US20040205325 Method and software for store multiplex operation
10/14/2004US20040205324 Method and software for partitioned floating-point multiply-add operation
10/14/2004US20040205323 Programmable processor and method for partitioned group element selection operation
10/14/2004US20040205308 Integrated memory having redundant units of memory cells and method for testing an integrated memory
10/14/2004US20040205306 Manipulating data for improving storage and transmission
10/14/2004US20040205305 Multiport memory architecture, devices and systems including the same, and methods of using the same
10/14/2004US20040205229 Method and apparatus for longest prefix matching in processing a forwarding information database
10/14/2004US20040205096 Programmable processor and system for partitioned floating-point multiply-add operation
10/14/2004US20040204891 Semiconductor memory device having a test mode for testing an operation state
10/14/2004US20040203711 Methods and apparatus for the utilization of core based nodes for state transfer
10/14/2004US20040202264 Multi-frequency synchronizing clock signal generator
10/14/2004US20040202263 Multi-frequency synchronizing clock signal generator
10/14/2004US20040202040 Virtual dual-port synchronous RAM architecture
10/14/2004US20040202036 High speed DRAM architecture with uniform access latency
10/14/2004US20040202035 Semiconductor memory storage
10/14/2004US20040202030 Mechanism for on-the-fly handling of unaligned memory accesses
10/14/2004US20040202029 Semiconductor memory device having column select line driving scheme for reducing skew between column select lines and column select line driving method thereof
10/14/2004US20040202028 Flash memory data bus for syncronous burst read page
10/14/2004US20040202027 Buffer amplifier architecture for semiconductor memory circuits
10/14/2004US20040202026 High speed latch and compare function
10/14/2004US20040202020 Semiconductor device
10/14/2004US20040201406 Ring-resister controlled DLL with fine delay line and direct skew sensing detector
10/14/2004US20040201405 Topology for providing clock signals to multiple circuit units on a circuit module
10/14/2004DE69333549T2 Halbleiterspeicheranordnung A semiconductor memory device
10/13/2004EP1104579B1 Memory supervision
10/13/2004CN2648726Y Robber looks and sound recording instrument
10/13/2004CN1537280A Adaptive throttling memory accesses, such as throttling RDRAm accesses in real-time system
10/13/2004CN1536674A Semiconductor storage
10/13/2004CN1536500A Medium processing equipment using external storage device
10/13/2004CN1171240C Apparatus for controlling circuit response during power-up
10/13/2004CN1171239C Semiconductor synchronous memory device and method for controlling same
10/13/2004CN1171238C Memory array with reduced charging current
10/13/2004CN1171234C Method and apparatus for a serial access memory
10/13/2004CN1171151C Method for recording data in nonvolatile storage
10/13/2004CN1171148C Reproducing device and reproducing method
10/12/2004US6804760 Method for determining a type of memory present in a system
10/12/2004US6804756 Synchronization circuit for read paths of an electronic memory
10/12/2004US6804743 Two step memory device command buffer apparatus and method and memory devices and computer systems using same
10/12/2004US6804685 Voice message managing method, in particular for a voice data recording/playing/editing electronic device
10/12/2004US6804305 Wide common mode range differential receiver
10/12/2004US6804166 Method and apparatus for operating a semiconductor memory at double data transfer rate
10/12/2004US6804165 Latency time switch for an S-DRAM
10/12/2004US6804164 Low-power consumption semiconductor memory device
10/12/2004US6804163 Semiconductor memory device for reducing chip size
10/12/2004US6804162 Read-modify-write memory using read-or-write banks
10/12/2004US6804161 Semiconductor device, refreshing method thereof, memory system, and electronic instrument
10/12/2004US6804160 Memory device and method of accessing a memory device
10/12/2004US6804158 Semiconductor circuit device with improved special mode
10/12/2004US6804157 Charging circuit and semiconductor memory device using the same
10/12/2004US6804153 Semiconductor memory device internally generating internal data read timing
10/12/2004US6804152 Method for manufacturing a printed board on which a semiconductor device having two modes is mounted
10/12/2004US6804146 Hybrid semiconductor—magnetic spin based memory
10/12/2004US6804145 Memory cell sensing system and method
10/12/2004US6804141 Dynamic reference voltage calibration integrated FeRAMS
10/12/2004US6804139 Method for non-destructive readout and apparatus for use with the method
10/12/2004US6804138 Addressing of memory matrix
10/12/2004US6803917 Checkerboard buffer using memory bank alternation
10/12/2004US6803794 Differential capacitance sense amplifier
10/12/2004US6803788 SSTL voltage translator with dynamic biasing
10/07/2004WO2004086406A1 Sense amplifier systems and a matrix-addressable memory device provided therewith
10/07/2004US20040199730 Device and method for controlling one or more memory modules
10/07/2004US20040199715 Method for performing a command cancel function in a dram
10/07/2004US20040199713 Synchronous flash memory with status burst output
10/07/2004US20040199710 Offset compensated sensing for magnetic random access memory
10/07/2004US20040199688 I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures
10/07/2004US20040198267 Methods and apparatus for equalization in single-ended chip-to-chip communication
10/07/2004US20040197084 Playback program
10/07/2004US20040196732 Multi-stage output multiplexing circuits and methods for double data rate synchronous memory devices
10/07/2004US20040196729 Method and system for accelerating coupling digital signals
10/07/2004US20040196725 Semiconductor memory device
10/07/2004US20040196721 Memory redundance circuit techniques
10/07/2004US20040196717 Method for reading and writing memory cells of spatial light modulators used in display systems
10/07/2004US20040196716 Semiconductor memory device
10/07/2004US20040196715 Pre-charge and sense-out circuit for differential type rom
10/07/2004US20040196712 Semiconductor memory device
10/07/2004US20040196711 Integrated semiconductor circuit having a cell array having a multiplicity of memory cells
10/07/2004US20040196707 Apparatus and method for managing bad blocks in a flash memory
10/07/2004US20040196706 Semiconductor storage device
10/07/2004US20040196705 Semiconductor memory device
10/07/2004US20040196699 Memory device and method of outputting data from a memory device
10/07/2004US20040196692 Semiconductor memory device with read and/or write column select gate
10/07/2004US20040196691 Memory device having different burst order addressing for read and write operations
10/07/2004US20040196690 Burst read addressing in a non-volatile memory device
10/07/2004US20040196687 Memory device and recording/reproducing apparatus using the same
10/07/2004US20040196170 Control systems having an analog control unit that generates an analog value responsive to a digital value and having twice the resolution of the least significant bit of the digital value and methods of operating the same
10/07/2004US20040196132 Transformer formed between two layout layers
10/07/2004US20040196080 Semiconductor integrated circuit device
10/07/2004US20040196079 Escalator code-based delay-locked loop apparatus and corresponding methods
10/07/2004US20040194713 Bolstered pet bed
10/07/2004DE10320792B3 Arrangement for synchronizing clock signals has phase comparison devices whose output signals control delay time of first delay device, delay time of variable part of second delay device respectively
10/07/2004DE10311373A1 Integrierter Speicher mit redundanten Einheiten von Speicherzellen und Verfahren zum Test eines integrierten Speichers Integrated memory having redundant units of memory cells and methods for testing an integrated memory
10/07/2004DE102004002219A1 Unterstütztes Speichersystem Supported storage system
10/07/2004CA2520492A1 Sense amplifier systems and a matrix-addressable memory device provided therewith
10/06/2004EP1465199A2 Memory device
10/06/2004EP1465198A2 Media-processing device using an external storage device
10/06/2004EP0995196B1 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
10/06/2004EP0904589B1 Floating gate memory device with low current page buffer
10/06/2004CN1534781A Semiconductor device containing changeable detdcting circuit and its starting method
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