| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 01/27/2005 | US20050018498 Process for controlling the read amplifiers of a memory and corresponding memory integrated circuit |
| 01/27/2005 | US20050018494 Double data rate (ddr) data strobe receiver |
| 01/27/2005 | US20050018477 Method and apparatus sensing a resistive memory with reduced power consumption |
| 01/27/2005 | US20050018470 Semiconductor memory devices for outputting bit cell data without separate reference voltage generator and related methods of outputting bit cell data |
| 01/27/2005 | US20050018469 Array transistor amplification method and apparatus for dynamic random access memory |
| 01/27/2005 | US20050018468 Ferroelectric memory |
| 01/27/2005 | US20050018464 High speed data bus |
| 01/27/2005 | US20050018090 Apparatus for preventing auto-convergence error in projection television receiver |
| 01/27/2005 | US20050017794 Ultra-low current band-gap reference |
| 01/27/2005 | US20050017327 High permeability composite films to reduce noise in high speed interconnects |
| 01/27/2005 | DE19882486B4 Synchroner, nicht-flüchtiger Seitenmodus-Speicher Synchronous, non-volatile page mode memory |
| 01/27/2005 | DE19601547B4 Speicherschaltung, Datensteuerschaltung der Speicherschaltung und Adressenzuweisungsschaltung der Speicherschaltung Memory circuit, data storage circuit of the control circuit and address assignment circuit of the memory circuit |
| 01/27/2005 | DE102004031959A1 Dynamic random access memory device, has read protection unit that supplies reset voltage that is higher than back-bias voltage to well region in response to externally supplied reset command |
| 01/27/2005 | DE102004019230A1 FeRAM memory device FeRAM memory device |
| 01/27/2005 | DE102004013110A1 Speichersystem Storage system |
| 01/27/2005 | DE102004008240A1 Verfahren und Vorrichtungen zum Bestimmen des Zustands eines Speicherelements Methods and apparatus for determining the state of a memory element |
| 01/27/2005 | DE102004008217A1 Schnittstellen für einen nicht-flüchtigen gepufferten Speicher Interfaces for a non-volatile buffer memory |
| 01/26/2005 | EP1501100A2 Nonvolatile memory device, memory system, and operating methods |
| 01/26/2005 | EP1501097A2 Memory circuit, display device and electronic equipment each comprising the same |
| 01/26/2005 | EP1500107A2 Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device |
| 01/26/2005 | EP1299885B1 Addressing of memory matrix |
| 01/26/2005 | EP0920699B1 Antifuse detect circuit |
| 01/26/2005 | CN1572002A Noise suppression for open bit line DRAM architectures |
| 01/26/2005 | CN1571070A 只读存储器设备 Read-only memory device |
| 01/25/2005 | US6848067 Multi-port scan chain register apparatus and method |
| 01/25/2005 | US6848040 Column address path circuit and method for memory devices having a burst access mode |
| 01/25/2005 | US6847583 Method of synchronizing read timing in a high speed memory system |
| 01/25/2005 | US6847580 Method of controlling data reading capable of increasing data transfer rate in SDRAM of the posted CAS standard |
| 01/25/2005 | US6847578 Semiconductor integrated circuit and data processing system |
| 01/25/2005 | US6847576 Layout structures of data input/output pads and peripheral circuits of integrated circuit memory devices |
| 01/25/2005 | US6847573 Synchronous SRAM-compatible memory device including DRAM array with internal refresh |
| 01/25/2005 | US6847569 Differential current sense amplifier |
| 01/25/2005 | US6847568 Sense amplifier configuration for a semiconductor memory device |
| 01/25/2005 | US6847567 Sense amplifier drive circuits responsive to predecoded column addresses and methods for operating the same |
| 01/25/2005 | US6847566 Method and circuit configuration for multiple charge recycling during refresh operations in a DRAM device |
| 01/25/2005 | US6847561 Semiconductor memory device |
| 01/25/2005 | US6847560 Method and circuit for generating constant slew rate output signal |
| 01/25/2005 | US6847559 Input buffer circuit of a synchronous semiconductor memory device |
| 01/25/2005 | US6847558 Integrated circuit and method of reading data from a memory device |
| 01/25/2005 | US6847555 Non-volatile semiconductor memory device reading and writing multi-value data from and into pair-cells |
| 01/25/2005 | US6847552 Flash array implementation with local and global bit lines |
| 01/25/2005 | US6847540 Semiconductor memory device and control method thereof |
| 01/25/2005 | US6847533 Current switching sensor detector |
| 01/25/2005 | US6847242 Escalator code-based delay-locked loop apparatus and corresponding methods |
| 01/25/2005 | US6846738 High permeability composite films to reduce noise in high speed interconnects |
| 01/25/2005 | CA2456968C Method of converting a series of m-bit information words to a modulated signal, method of producing a record carrier, coding device, decoding device, recording device, reading device, signal, as well as a record carrier |
| 01/20/2005 | WO2005006822A2 Battery pack with built-in communication port |
| 01/20/2005 | US20050015558 Method and apparatus for generating a write mask key |
| 01/20/2005 | US20050015553 Methods, circuits, and systems for utilizing idle time in dynamic frequency scaling cache memories |
| 01/20/2005 | US20050015539 Memory system and memory card |
| 01/20/2005 | US20050015530 MP3 voice recording/playing device |
| 01/20/2005 | US20050013191 Memory device having repeaters |
| 01/20/2005 | US20050013189 Regulating voltages in semiconductor devices |
| 01/20/2005 | US20050013184 Dual loop sensing scheme for resistive memory elements |
| 01/20/2005 | US20050013182 Systems and methods for sensing a memory element |
| 01/20/2005 | US20050013181 Assisted memory device with integrated cache |
| 01/20/2005 | US20050013180 Memory circuit, display device and electronic equipment each comprising the same |
| 01/20/2005 | US20050013178 Synchronous semiconductor memory device having stable data output timing |
| 01/20/2005 | US20050013177 Low power register apparatus having a two-way gating structure and method thereof |
| 01/20/2005 | US20050013175 Semiconductor memory device having over-driving scheme |
| 01/20/2005 | US20050013169 Nonvolatile semiconductor memory device |
| 01/20/2005 | US20050013162 Nonvolatile semiconductor memory device and one-time programming control method thereof |
| 01/20/2005 | US20050013159 Semiconductor integrated circuit device |
| 01/20/2005 | US20050012533 Semiconductor integrated circuit device |
| 01/20/2005 | DE10328385A1 Memory system, e.g. DRAM, performs data transmission between control device and memory devices via two internal data busses, and only via first data bus for further internal data packets |
| 01/20/2005 | DE102004029846A1 Integrated circuit memory device, has column select IO blocks and N-type sense amplifier blocks arranged in zig-zag layout pattern that spans two rows of zeroth sense amplifier region |
| 01/20/2005 | CA2530889A1 Battery pack with built-in communication port |
| 01/19/2005 | EP1498906A1 A redundancy scheme for an integrated memory circuit |
| 01/19/2005 | EP1498905A2 Operating voltage selection circuit for non-volatile semiconductor memories |
| 01/19/2005 | EP1498903A2 High speed data access memory arrays |
| 01/19/2005 | EP1497733A1 Destructive-read random access memory system buffered with destructive-read memory cache |
| 01/19/2005 | CN2673012Y Cell phone with mobile storage function |
| 01/19/2005 | CN1568523A Sense amplifier and architecture for open digit arrays |
| 01/19/2005 | CN1568522A Dynamic column block selection |
| 01/19/2005 | CN1568521A Adjustable memory self-timing circuit |
| 01/19/2005 | CN1567477A SRAM interface compatible delayed reading/storing mode of DRAM |
| 01/19/2005 | CN1567476A High speed big block data writing method for flash memory |
| 01/19/2005 | CN1567475A Memory element with built-in error connecting function |
| 01/19/2005 | CN1567338A Image and sound information operating system |
| 01/19/2005 | CN1185658C Memory array with address scrambling |
| 01/19/2005 | CN1185657C Input device and output device |
| 01/19/2005 | CN1185580C Semiconductor integrated circuit and data processing system |
| 01/18/2005 | US6845433 Memory device having posted write per command |
| 01/18/2005 | US6845414 Apparatus and method of asynchronous FIFO control |
| 01/18/2005 | US6845407 Semiconductor memory device having externally controllable data input and output mode |
| 01/18/2005 | US6845059 High performance gain cell architecture |
| 01/18/2005 | US6845058 Serial access memory |
| 01/18/2005 | US6845055 Semiconductor memory capable of transitioning from a power-down state in a synchronous mode to a standby state in an asynchronous mode without setting by a control register |
| 01/18/2005 | US6845052 Dual reference cell sensing scheme for non-volatile memory |
| 01/18/2005 | US6845051 Semiconductor memory device and data access method for semiconductor memory device |
| 01/18/2005 | US6845050 Signal delay control circuit in a semiconductor memory device |
| 01/18/2005 | US6845049 Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time |
| 01/18/2005 | US6845048 System and method for monitoring internal voltages on an integrated circuit |
| 01/18/2005 | US6845047 Read circuit of nonvolatile semiconductor memory |
| 01/18/2005 | US6845041 Non-volatile semiconductor memory device with accelerated column scanning scheme |
| 01/18/2005 | US6845039 Programming methods for multi-level flash EEPROMS |
| 01/18/2005 | US6845037 Reference cells for TCCT based memory cells |
| 01/18/2005 | US6844926 Semiconductor integrated circuit |
| 01/18/2005 | US6844754 Data bus |
| 01/18/2005 | US6844256 High permeability composite films to reduce noise in high speed interconnects |