G11C 7 - Arrangements for writing information into, or reading information out from, a digital store

Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
12/2004
12/16/2004	US20040252560 Multifunctional flash memory drive
12/16/2004	US20040252559 Transplanted magnetic random access memory (MRAM) devices on thermally-sensitive substrates using laser transfer and method for making the same
12/16/2004	US20040252557 High reliable reference current generator for mram
12/16/2004	US20040252552 Nonvolatile semiconductor memory with a page mode
12/16/2004	US20040252550 Integrated circuit and method for operating an integrated circuit
12/16/2004	US20040252548 Semiconductor memory device
12/16/2004	US20040252547 Concurrent Processing Memory
12/16/2004	US20040252543 Adjusting the frequency of an oscillator for use in a resistive sense amp
12/16/2004	US20040252542 Ferroelectric memory device
12/16/2004	US20040251940 Semiconductor integrated circuit controlling output impedance and slew rate
12/16/2004	US20040251939 Devices for synchronizing clock signals
12/16/2004	US20040251933 Apparatus for generating driving voltage for sense amplifier in a memory device
12/16/2004	DE69133365T2 Halbleiterspeicher mit sequenzgetakteten Zugriffscodes zum Eintritt in den Prüfmodus Semiconductor memory with sequence clocked access code to enter the test mode
12/16/2004	DE202004015751U1 Portable MP3 player for use with motor vehicle audio system, emits a signal to blanket a specific channel on the vehicle FM receiver to transfer audio
12/16/2004	DE10323244A1 Integrierte Speicher-Schaltungsanordnung, insbesondere UCP-Flash-Speicher Integrated memory circuit arrangement, in particular flash memory UCP
12/16/2004	DE10323237A1 Modifying time period between execution operations in DRAM, by changing set time period in direction of real time period selected during test mode
12/16/2004	DE10322541A1 Memory chip with integral address scrambling unit whereby the address can be scrambled in different ways according to the address control bits
12/16/2004	DE10320793A1 Latch or phase detector circuit for DRAM data storage uses flip flop stage and cascaded NAND gates to give output depending on clock and data state change phase
12/15/2004	EP1486984A1 Data storage circuit, data write method in the data storage circuit, and data storage device
12/15/2004	EP1486982A2 Latency control circuit and method of latency control
12/15/2004	EP1486878A2 Semiconductor memory device and information processing unit
12/15/2004	EP1486877A2 Semiconductor memory device and information processing unit
12/15/2004	EP1485920A1 Increasing the read signal in ferroelectric memories
12/15/2004	EP1485919A2 Method and system for maximizing dram memory bandwidth
12/15/2004	EP1485918A1 Memory module with playback mode
12/15/2004	EP1485259A1 Device, system and method for data exchange
12/15/2004	CN1555561A Concept for a secure data communication between electronic devices
12/15/2004	CN1555558A Apparatus and method for a memory storage cell leakage cancellation scheme
12/15/2004	CN1555557A Writing device, semiconductor memory card, program, and method
12/15/2004	CN1180435C Zero power high speed configuration memory
12/14/2004	US6832327 Apparatus and method for providing an external clock from a circuit in sleep mode in a processor-based system
12/14/2004	US6832325 Device on a source synchronous bus sending data in quadrature phase relationship and receiving data in phase with the bus clock signal
12/14/2004	US6832293 Audio playback apparatus and method for resuming interrupted playback recording
12/14/2004	US6832177 Method of addressing individual memory devices on a memory module
12/14/2004	US6831873 Independent in-line SDRAM control
12/14/2004	US6831871 Stable memory cell read
12/14/2004	US6831870 Semiconductor memory
12/14/2004	US6831867 Semiconductor device having mechanism capable of high-speed operation
12/14/2004	US6831866 Method and apparatus for read bitline clamping for gain cell DRAM devices
12/14/2004	US6831859 Non-volatile semiconductor memory for storing initially-setting data
12/14/2004	US6831853 Apparatus for cleaning a substrate
12/14/2004	US6831852 Semiconductor memory device having a latch circuit and storage capacitor
12/14/2004	US6831851 Mask ROM
12/14/2004	US6831651 Checkerboard buffer
12/14/2004	US6831650 Checkerboard buffer using sequential memory locations
12/14/2004	US6831649 Two-dimensional buffer pages using state addressing
12/14/2004	US6831478 Open drain type output buffer
12/14/2004	US6831320 Memory cell configuration for a DRAM memory with a contact bit terminal for two trench capacitors of different rows
12/14/2004	US6831317 System with meshed power and signal buses on cell array
12/09/2004	WO2004107349A1 Integrated charge sensing scheme for resistive memories
12/09/2004	WO2004107348A1 Circuit configuration for a current switch of a bit/word line of a mram device
12/09/2004	WO2004107076A1 Floating-gate reference circuit
12/09/2004	US20040250183 System architecture and method for three-dimensional memory
12/09/2004	US20040250091 Microprocessor apparatus and method for optimizing block cipher cryptographic functions
12/09/2004	US20040250040 Pipline memory device
12/09/2004	US20040250011 Storage device capable of increasing transmission speed
12/09/2004	US20040250010 Storage device available for increasing storage capacity
12/09/2004	US20040247284 Data processing unit and method, and program
12/09/2004	US20040246811 Adjustable clock driver circuit
12/09/2004	US20040246810 Apparatus and method for reducing power consumption by a data synchronizer
12/09/2004	US20040246809 Integrated circuit including processor and crystal oscillator emulator
12/09/2004	US20040246808 Writing driver circuit of phase-change memory
12/09/2004	US20040246807 Multi-port memory device with stacked banks
12/09/2004	US20040246804 Device and method for pulse width control in a phase change memory device
12/09/2004	US20040246801 Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation
12/09/2004	US20040246800 Dynamically unbalanced sense amplifier
12/09/2004	US20040246799 Memory devices having bit line precharge circuits with off current precharge control and associated bit line precharge methods
12/09/2004	US20040246796 Row-column repair technique for semiconductor memory arrays
12/09/2004	US20040246793 Semiconductor memory device
12/09/2004	US20040246792 Integrated memory circuit having a redundancy circuit and a method for replacing a memory area
12/09/2004	US20040246790 Driving a DRAM sense amplifier having low threshold voltage PMOS transistors
12/09/2004	US20040246786 Memory channel having deskew separate from redrive
12/09/2004	US20040246785 Memory channel with redundant presence detect
12/09/2004	US20040246784 Nonvolatile semiconductor memory device
12/09/2004	US20040246783 High burst rate write data paths for integrated circuit memory devices and methods of operating same
12/09/2004	US20040246782 Apparatus and method for a radiation resistant latch
12/09/2004	US20040246771 Method of transferring data
12/09/2004	US20040246258 Swapped pixel pages
12/09/2004	US20040245547 Ultra low-cost solid-state memory
12/09/2004	DE19744277B4 Medium-Aufnahmevorrichtung zum Aufnehmen und Wiedergeben von mit Eingabe-/Wiedergabesignalen synchronisierten Zeitcodes in und von Aufnahmemedien mit einem UTOC-Bereich sowie ein Aufnahmemedium mit einem UTOC-Bereich Medium recording apparatus for recording and reproducing synchronized with input / playback time code signals to and from recording media with a TOC area as well as a recording medium having a TOC area
12/09/2004	DE10297097T5 Schmelzprogrammierbare E/A-Organisation Melting Programmable I / O organization
12/09/2004	DE102004023407A1 Integriertes Selbsttestsystem und -verfahren Built-in self-test system and method
12/09/2004	DE102004022355A1 Halbleiterbaustein mit bidirektionalem Eingabe-/Ausgabeanschluss und zugehöriges Verfahren zum Ein- und Ausgeben von Daten Semiconductor device with bidirectional input / output port and associated method for inputting and outputting data
12/09/2004	DE102004020038A1 Memory module e.g. dynamic random access memory (DRAM) for motherboard, comprises several DRAM chips stacked on input-output chip, connected through penetration electrodes
12/08/2004	EP1484764A1 Method for generating a reference current for sense amplifiers connected to cells of a memory matrix, particularly in big-sized flash memories, and corresponding generator
12/08/2004	CN1554098A Method and apparatus for automatic equalization mode activation
12/08/2004	CN1554097A Memory device having different burst order addressing for read and write operations
12/08/2004	CN1179364C Semiconductor memory device
12/08/2004	CN1179363C Operation method of fast erasable and rewritable memory with symmetrical double-channel
12/08/2004	CN1179362C Period idependent data output to reflective clock tracking circuit
12/07/2004	US6829682 Destructive read architecture for dynamic random access memories
12/07/2004	US6829677 Method and apparatus for preserving the contents of synchronous DRAM through system reset
12/07/2004	US6829316 Input circuit and output circuit
12/07/2004	US6829195 Semiconductor memory device and information processing system
12/07/2004	US6829191 Magnetic memory equipped with a read control circuit and an output control circuit
12/07/2004	US6829190 Method and system for programming a memory device
12/07/2004	US6829189 Semiconductor memory device and bit line sensing method thereof
12/07/2004	US6829188 Dual loop sensing scheme for resistive memory elements
12/07/2004	US6829187 Memory device
12/07/2004	US6829186 Semiconductor integrated circuit

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