Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
02/2005
02/08/2005US6853578 Pulse driven single bit line SRAM cell
02/08/2005US6853576 Semiconductor device, method for fabricating the same, and method for driving the same
02/08/2005US6853572 Methods and apparatuses for a ROM memory array having twisted source or bit lines
02/08/2005US6853317 Circuit and method for generating mode register set code
02/08/2005US6851552 Containers with additional functionality
02/03/2005WO2005010758A1 High-speed data-rate converting and switching circuit
02/03/2005WO2004073022A3 Dram output circuitry supporting sequential data capture to reduce core access times
02/03/2005US20050028125 Layout method for miniaturized memory array area
02/03/2005US20050028019 Delay locked loop with improved jitter and clock delay compensating method thereof
02/03/2005US20050026336 Current limiting antifuse programming path
02/03/2005US20050024985 Delay locked loop control circuit
02/03/2005US20050024984 Data input circuit and method for synchronous semiconductor memory device
02/03/2005US20050024980 Synchronous flash memory with non-volatile mode register
02/03/2005US20050024975 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
02/03/2005US20050024973 Current limiting antifuse programming path
02/03/2005US20050024972 Programmable DQS preamble
02/03/2005US20050024970 Device having a memory array storing each bit in multiple memory cells
02/03/2005US20050024967 Semiconductor memory device
02/03/2005US20050024966 Amplifier and semiconductor storage device using the same
02/03/2005US20050024965 Dynamic semiconductor storage device and method of reading and writing operations thereof
02/03/2005US20050024963 Semiconductor memory module
02/03/2005US20050024961 Nonvolatile memory cells with buried channel transistors
02/03/2005US20050024957 Magnetic hard disk recording head with self-compensating thermal expansion
02/03/2005US20050024956 Column redundancy for digital multilevel nonvolatile memory
02/03/2005US20050024951 Voltage and temperature compensated pulse generator
02/03/2005US20050024950 Readout circuit for semiconductor storage device
02/03/2005US20050024949 Semiconductor integrated circuit device
02/03/2005US20050024947 Data output circuits for synchronous integrated circuit memory devices
02/03/2005US20050024942 Semiconductor memory device having a burst continuous read function
02/03/2005US20050024936 Vertical gain cell
02/03/2005US20050024932 Method for writing data to a semiconductor memory comprising a peripheral circuit section and a memory core section including a memory cell
02/03/2005US20050024926 Deskewing data in a buffer
02/03/2005US20050024923 Gain cell memory having read cycle interlock
02/03/2005US20050024368 Two dimensional buffer pages
02/03/2005US20050024108 System and method to improve the efficiency of synchronous mirror delays and delay locked loops
02/03/2005US20050024096 Clock enable buffer for entry of self-refresh mode
02/03/2005US20050024095 Low jitter input buffer with small input signal swing
02/03/2005US20050024091 Circuit and method for improving noise tolerance in multi-threaded memory circuits
02/03/2005US20050023650 Capacitive techniques to reduce noise in high speed interconnections
02/03/2005DE69333631T2 Halbleiterspeicheranordnung A semiconductor memory device
02/03/2005DE10245536B4 Kalibrieren von Halbleitereinrichtungen mittels einer gemeinsamen Kalibrierreferenz Calibration of semiconductor devices by means of a joint calibration reference
02/03/2005DE10015253B4 Halbleiter-Speichervorrichtung und Schreibdaten-Maskierungsverfahren dafür The semiconductor memory device and write data masking method thereof
02/02/2005EP1440446A4 Non-volatile memory with temperature-compensated data read
02/02/2005CN1575495A Memory arrangement
02/02/2005CN1574724A 采样频率变换装置及采样频率变换方法 Apparatus and method for converting the sampling frequency of sampling frequency conversion
02/02/2005CN1574356A Ultra low-cost solid-state memory
02/02/2005CN1574102A Method for testing a memory device
02/02/2005CN1574100A 半导体存储设备 The semiconductor memory device
02/02/2005CN1574094A Memory device
02/02/2005CN1574093A Device and method for pulse width control in a phase change memory device
02/02/2005CN1574089A 电流模式输出驱动器 Current-mode output driver
02/02/2005CN1574088A Apparatus for generating driving voltage for sense amplifier in a memory device
02/02/2005CN1574087A Latency control circuit and method of latency control
02/02/2005CN1574084A Memory devices having bit line precharge circuits and associated bit line precharge methods
02/02/2005CN1574073A Nonvolatile ferroelectric memory device having multi-bit control function
02/02/2005CN1574070A MRAM having memory cell array in which cross-point memory cells are arranged by hierarchical bit line scheme and data read method thereof
02/02/2005CN1574063A Memory device with selectively connectable segmented bit line member and method of driving the same
02/02/2005CN1187832C 半导体存储器件 The semiconductor memory device
02/02/2005CN1187825C Semiconductor storing device with shorter time delay of data transmission
02/02/2005CN1187814C Input/output unit configuring method and semi-conductor equipment
02/02/2005CN1187759C Semiconductor memory with built-in row buffer and method of driving the same
02/02/2005CN1187757C Synchronization device for synchronous dynamic random-access memory
02/02/2005CN1187756C Semiconductor memory card, playback appts. recording appts. playback method, recording method, and computer-readable recording medium
02/01/2005US6851026 Synchronous flash memory with concurrent write and read operation
02/01/2005US6851018 Exchanging operation parameters between a data storage device and a controller
02/01/2005US6851016 System latency levelization for read data
02/01/2005US6850625 Information storage method, information storage device and recording medium
02/01/2005US6850459 Synchronous semiconductor memory device allowing adjustment of data output timing
02/01/2005US6850458 Controlling data strobe output
02/01/2005US6850457 Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMS
02/01/2005US6850456 Subarray control and subarray cell access in a memory module
02/01/2005US6850454 Semiconductor memory device with reduced current consumption during standby state
02/01/2005US6850447 Nonvolatile ferroelectric memory device having multi-bit control function
02/01/2005US6850446 Memory cell sensing with low noise generation
02/01/2005US6850444 Data input device of a DDR SDRAM
02/01/2005US6850241 Swapped pixel pages
02/01/2005US6850108 Input buffer
02/01/2005US6850107 Variable delay circuit and method, and delay locked loop, memory device and computer system using same
02/01/2005US6850096 Interpolating sense amplifier circuits and methods of operating the same
02/01/2005US6850093 Circuit and method for improving noise tolerance in multi-threaded memory circuits
02/01/2005US6849958 Semiconductor latches and SRAM devices
01/2005
01/27/2005WO2005008893A1 Semiconductor integrated circuit
01/27/2005WO2005008675A1 Compensating a long read time of a memory device in data comparison and write operations
01/27/2005WO2005008674A2 Semiconductor memory having a short effective word-line cycle time and data readout method for said semi-conductor memory
01/27/2005WO2005008673A1 Data strobe synchronization circuit and method for double data rate, multi-bit writes
01/27/2005WO2004032146A3 Programmable magnetic memory device fp-mram
01/27/2005US20050021905 Flash memory system and data writing method thereof
01/27/2005US20050021899 Access of two synchronous busses with asynchronous clocks to a synchronous single port ram
01/27/2005US20050018528 Memory arrangement for processing data, and method
01/27/2005US20050018527 Non-volatile memory control
01/27/2005US20050018524 Synchronous flash memory command sequence
01/27/2005US20050018518 Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells
01/27/2005US20050018517 Fuse blowing interface for a memory chip
01/27/2005US20050018515 Stress balanced semiconductor packages, method of fabrication and modified mold segment
01/27/2005US20050018513 Temperature detection circuit and temperature detection method
01/27/2005US20050018512 Integrated charge sensing scheme for resistive memories
01/27/2005US20050018511 Semiconductor memory device which selectively controls a local input/output line sense amplifier
01/27/2005US20050018510 Sense amplifier with offset cancellation and charge-share limited swing drivers
01/27/2005US20050018507 Circuit and method for controlling an access to an integrated memory
01/27/2005US20050018506 Sense amp equilibration device