G11C 7 - Arrangements for writing information into, or reading information out from, a digital store

Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
11/2004
11/25/2004	US20040233757 Magnetic memory device, a method for manufacturing a magnetic memory device, and an integrated circuit device including such magnetic memory device
11/25/2004	US20040233754 Semiconductor memory device having sense amplifier and method for overdriving the sense amplifier
11/25/2004	US20040233753 Semiconductor memory
11/25/2004	US20040233747 RAM store and control method therefor
11/25/2004	US20040233746 Magnetic memory device and method for magnetic reading and writing
11/25/2004	US20040233740 Semiconductor memory
11/25/2004	US20040233737 Circuit arrangement and method for setting a voltage supply for a read/write amplifier of an integrated memory
11/25/2004	US20040233736 Nonvolatile switch, in particular for high-density nonvolatile programmable-logic devices
11/25/2004	US20040233735 Current mode output driver
11/25/2004	US20040233734 Semiconductor memory device and method for writing and reading data
11/25/2004	US20040233733 Memory data interface
11/25/2004	US20040233721 Semiconductor memory device capable of being mounted on a single package regardless of bit organization
11/25/2004	US20040233720 Non-volatile semiconductor memory device
11/25/2004	US20040233714 Semiconductor memory device and portable electronic apparatus
11/25/2004	US20040233709 MRAM having memory cell array in which cross-point memory cells are arranged by hierarchical bit line scheme and data read method thereof
11/25/2004	US20040233700 Register controlled DLL for reducing current consumption
11/25/2004	US20040233696 Nonvolatile ferroelectric memory device having multi-bit control function
11/25/2004	US20040233645 Portable data storage device
11/25/2004	US20040233206 Pixel pages optimized for GLV
11/25/2004	US20040232941 Input circuit for receiving a signal at an input on an integrated circuit
11/25/2004	US20040232474 Nonvolatile semiconductor memory device
11/25/2004	US20040231495 Digital music conversion device
11/25/2004	EP1620859A2 Reference current generator, and method of programming, adjusting and/or operating same
11/25/2004	DE10318771A1 Integrated memory circuit with redundancy circuit for replacing memory area with address by redundant memory area has deactivation memory element for enabling/inhibiting replacement of memory area
11/25/2004	DE102004019672A1 Vorrichtung zum Verhindern von Autokonvergenzfehlern in Projektionsfernsehempfängern A device for preventing auto convergence errors in projection television receivers
11/25/2004	DE10012121B4 Signalumwandlungsvorrichtung Signal conversion means
11/24/2004	EP1480226A2 MRAM having memory cell array in which cross-point memory cells are arranged by hierarchical bit line scheme and data read method thereof
11/24/2004	EP1479006A1 A memory and an adaptive timing system for controlling access to the memory
11/24/2004	CN1549972A 智能存储器 Intelligent memory
11/24/2004	CN1549273A Precharge and detecting circuit for differential read-only storage
11/24/2004	CN1549121A Hiding error detecting/correcting latency in dynamic random access memory (DRAM)
11/23/2004	US6823434 System and method for resetting and initializing a fully associative array to a known state at power on or through machine specific state
11/23/2004	US6823407 Output data path capable of multiple data rates
11/23/2004	US6822925 Synchronous mirror delay with reduced delay line taps
11/23/2004	US6822924 Synchronous semiconductor memory device having clock synchronization circuit and circuit for controlling on/off of clock tree of the clock synchronization circuit
11/23/2004	US6822923 RAM memory circuit and method for controlling the same
11/23/2004	US6822922 Clock synchronous circuit
11/23/2004	US6822919 Single ended output sense amplifier circuit with reduced power consumption and noise
11/23/2004	US6822917 Data write circuit in memory system and data write method
11/23/2004	US6822915 Method and circuit for charging a signal voltage through a semiconductor memory device
11/23/2004	US6822914 Circuits and methods for generating high frequency extended test pattern data from low frequency test pattern data input to an integrated circuit memory device
11/23/2004	US6822913 Integrated memory and method for operating an integrated memory
11/23/2004	US6822911 Dynamic column block selection
11/23/2004	US6822908 Synchronous up/down address generator for burst mode read
11/23/2004	US6822907 Nonvolatile semiconductor memory device and data readout method for the same
11/23/2004	US6822906 Sense amplifier structure for multilevel non-volatile memory devices and corresponding reading method
11/23/2004	US6822904 Fast sensing scheme for floating-gate memory cells
11/23/2004	US6822900 Non-volatile semiconductor memory device
11/23/2004	US6822895 Magnetic memory device
11/23/2004	US6822891 Ferroelectric memory device
11/23/2004	US6822885 High speed latch and compare function
11/23/2004	US6822490 Data output circuit for reducing skew of data signal
11/23/2004	US6822335 Method for arranging wiring line including power reinforcing line and semiconductor device having power reinforcing line
11/18/2004	WO2004100267A1 Cubic memory array
11/18/2004	WO2004100169A2 Mram architecture with a bit line located underneath the magnetic tunneling junction device
11/18/2004	WO2004099994A1 Sampling tuning system
11/18/2004	US20040230932 Method for controlling semiconductor chips and control apparatus
11/18/2004	US20040230930 Short edge management in rule based OPC
11/18/2004	US20040230870 Built-in self test system and method
11/18/2004	US20040228483 Apparatus and method for performing transparent cipher feedback mode cryptographic functions
11/18/2004	US20040228481 Apparatus and method for performing transparent block cipher cryptographic functions
11/18/2004	US20040228203 Data input device in semiconductor memory device
11/18/2004	US20040228199 Semiconductor integrated circuit
11/18/2004	US20040228196 Memory devices, systems and methods using selective on-die termination
11/18/2004	US20040228195 Bias sensing in DRAM sense amplifiers
11/18/2004	US20040228193 Semiconductor storage device, semiconductor device, manufacturing method of semiconductor storage device, and mobile electronic device
11/18/2004	US20040228191 Circuit and method for fuse disposing in a semiconductor memory device
11/18/2004	US20040228188 Flash memory device with burst read mode of operation
11/18/2004	US20040228186 Analysis method for semiconductor device, analysis system and a computer program product
11/18/2004	US20040228185 Non-volatile semiconductor memory device and method of manufacturing the same
11/18/2004	US20040228176 Semiconductor memory device having a hierarchical I/O structure
11/18/2004	US20040228170 Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices
11/18/2004	US20040228162 Sense amplifier for low-supply-voltage nonvolatile memory cells
11/18/2004	US20040227543 Sense amplifying circuit for a semiconductor memory with improved data read ability at a low supply voltage
11/18/2004	US20040227166 Reference current generator, and method of programming, adjusting and/or operating same
11/18/2004	DE19828402B4 Halbleiterspeicher Semiconductor memory
11/18/2004	DE10361692A1 Speichervorrichtung mit Testmodus zum Steuern einer Bitleitungs-Erfassungsspannenzeit Storage device with test mode for controlling a bit line sense span of time
11/18/2004	DE10361677A1 Halbleitereinrichtung zur Domäne-Kreuzung Semiconductor device for domain-crossing
11/18/2004	DE10361675A1 Verfahren zum Lesen einer Bitleitung mit gleichbleibender Lesezeitspanne und Speichervorrichtung dafür A method of reading a bit line with a constant period and reading memory apparatus therefor
11/18/2004	DE10361662A1 Semiconductor memory device, has repair circuit controller in response to delayed control signal for generating one of repair address and normal address enable signals based on comparison of address with stored repair address
11/18/2004	DE10317162A1 Dynamic RAM storage device for row-cycle time and read latency in semiconductors has a cell field with multiple memory cells, a control device and an electrical bias
11/18/2004	DE102004015534A1 Speicherbauelement und Verfahren zum Ausgeben von Daten aus einem Speicherbauelement Memory device and method for outputting data from a memory device
11/18/2004	DE10149590B4 Halbleiterbaustein mit konfigurierbarer Datenbreite eines Ausgangsbusses und Gehäuseanordnung mit einem Halbleiterbaustein Semiconductor device with configurable data width of an output bus and housing assembly with a semiconductor device
11/18/2004	DE10136853B4 Verfahren zur Datenkommunikation mehrerer Halbleiterspeicherbausteine mit einem Controllerbaustein und dafür eingerichteter Halbleiterspeicherbaustein Method for data communication of multiple semiconductor memory devices with a controller chip and appropriately configured semiconductor memory device
11/18/2004	CA2522393A1 Sampling tuning system
11/17/2004	EP1477989A1 Clock suspending circuitry
11/17/2004	EP1477901A1 External connection device, host device, and data communication system
11/17/2004	EP1477900A2 A data processing structure unit
11/17/2004	EP1476875A1 Mram without isolation devices
11/17/2004	EP1476812A1 Pipelined parallel programming operation in a non-volatile memory system
11/17/2004	EP1476805A1 Direct memory swapping between nand flash and sram with error correction coding
11/17/2004	EP1264313B1 Memory module with hierarchical functionality
11/16/2004	US6820179 Semiconductor device and data processing system
11/16/2004	US6820163 Buffering data transfer between a chipset and memory modules
11/16/2004	US6819626 Semiconductor integrated circuit device
11/16/2004	US6819625 Memory device
11/16/2004	US6819624 Latency time circuit for an S-DRAM
11/16/2004	US6819623 Integrated circuit memory devices having efficient column select signal generation during normal and refresh modes of operation and methods of operating same
11/16/2004	US6819622 Write and erase protection in a synchronous memory
11/16/2004	US6819617 System and method for performing partial array self-refresh operation in a semiconductor memory device

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