| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 01/06/2005 | US20050002243 Reduced power redundancy address decoder and comparison circuit |
| 01/06/2005 | US20050002242 Methods and apparatus for the utilization of core based nodes for state transfer |
| 01/06/2005 | US20050002232 Segmented metal bitlines |
| 01/06/2005 | US20050002225 Semiconductor memory device |
| 01/06/2005 | US20050002224 Semiconductor integrated circuit device |
| 01/06/2005 | US20050002223 Output driver impedance control for addressable memory devices |
| 01/06/2005 | US20050002219 Methods and devices for preventing data stored in memory from being read out |
| 01/06/2005 | US20050001667 Delay circuit with more-responsively adapting delay time |
| 01/06/2005 | US20050001244 Semiconductor memory device having externally controllable data input and output mode |
| 01/06/2005 | CA2528804A1 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same |
| 01/05/2005 | EP1494243A2 Memory system having data inversion and data inversion method for a memory system |
| 01/05/2005 | EP1494242A1 Method and memory system having mode selection between dual data strobe mode and single data strobe mode with data inversion |
| 01/05/2005 | EP1493158A1 Single-ended current sense amplifier |
| 01/05/2005 | CN1560868A Implementing asynchronous first-in first-out data transmission by double-port direct access storage device |
| 01/05/2005 | CN1183596C Synchronous data collecting circuit with low voltage level and method therefor |
| 01/05/2005 | CN1183544C Electric current driving device for magnetic-resistance storage |
| 01/05/2005 | CN1183543C Dictation device for storage of speech signals |
| 01/04/2005 | US6839860 Capture clock generator using master and slave delay locked loops |
| 01/04/2005 | US6839859 Semiconductor integrated circuit having clock synchronous type circuit and clock non-synchronous type circuit |
| 01/04/2005 | US6839797 Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem |
| 01/04/2005 | US6839786 Information processing system with memory modules of a serial bus architecture |
| 01/04/2005 | US6839301 Method and apparatus for improving stability and lock time for synchronous circuits |
| 01/04/2005 | US6839300 Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs |
| 01/04/2005 | US6839299 Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells |
| 01/04/2005 | US6839296 Control clocks generator and method thereof for a high speed sense amplifier |
| 01/04/2005 | US6839295 Semiconductor memory device and method of reading data from the semiconductor memory device |
| 01/04/2005 | US6839294 Memory device with high charging voltage bit line |
| 01/04/2005 | US6839291 Method for controlling column decoder enable timing in synchronous semiconductor device and apparatus thereof |
| 01/04/2005 | US6839290 Method, apparatus, and system for high speed data transfer using source synchronous data strobe |
| 01/04/2005 | US6839288 Latch scheme with invalid command detector |
| 01/04/2005 | US6839286 Semiconductor device with programmable impedance control circuit |
| 01/04/2005 | US6839282 Semiconductor nonvolatile memory for performing read operations while performing write operations |
| 01/04/2005 | US6839279 Nonvolatile semiconductor memory device |
| 01/04/2005 | US6839268 Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system |
| 01/04/2005 | US6839267 Structure and method of multiplexing bitline signals within a memory array |
| 01/04/2005 | US6839266 Memory module with offset data lines and bit line swizzle configuration |
| 01/04/2005 | US6839261 Semiconductor memory device |
| 01/04/2005 | US6838917 Circuit configuration for processing data, and method for identifying an operating state |
| 01/04/2005 | US6838915 Input and output circuit of semiconductor device |
| 01/04/2005 | US6838901 Semiconductor integrated circuits with power reduction mechanism |
| 01/04/2005 | US6838723 Merged MOS-bipolar capacitor memory cell |
| 01/04/2005 | US6838712 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM |
| 01/04/2005 | US6838337 Sense amplifier and architecture for open digit arrays |
| 12/30/2004 | US20040268207 Systems and methods for implementing a rate converting, low-latency, low-power block interleaver |
| 12/30/2004 | US20040268081 Apparatus and method for storing digital data |
| 12/30/2004 | US20040268075 Sensing word groups in a memory |
| 12/30/2004 | US20040268065 Methods and apparatuses for determining the state of a memory element |
| 12/30/2004 | US20040268046 Nonvolatile buffered memory interface |
| 12/30/2004 | US20040268038 Storage system |
| 12/30/2004 | US20040268029 Method and apparatus for using SDRAM to read and write data without latency |
| 12/30/2004 | US20040268027 Semiconductor memory device, page buffer resource assigning method and circuit therefor, computer system and mobile electronic device |
| 12/30/2004 | US20040268025 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein |
| 12/30/2004 | US20040268020 Storage device for a multibus architecture |
| 12/30/2004 | US20040268016 Synchronous memory device having advanced data align circuit |
| 12/30/2004 | US20040267787 System and method for performing a warm shutdown and restart of a buffer pool |
| 12/30/2004 | US20040267520 Audio playback/recording integrated circuit with filter co-processor |
| 12/30/2004 | US20040267409 Method and apparatus for memory bandwidth thermal budgetting |
| 12/30/2004 | US20040266027 Method and system for fast data access using a memory array |
| 12/30/2004 | US20040264291 Data pass control device for masking write ringing in DDR SDRAM and method thereof |
| 12/30/2004 | US20040264290 Method for masking ringing in ddr sdram |
| 12/30/2004 | US20040264289 Timer lockout circuit for synchronous applications |
| 12/30/2004 | US20040264288 Timing circuit and method of changing clock period |
| 12/30/2004 | US20040264286 Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device |
| 12/30/2004 | US20040264282 Predecode column architecture and method |
| 12/30/2004 | US20040264280 Subarray control and subarray cell access in a memory module |
| 12/30/2004 | US20040264279 High performance gain cell architecture |
| 12/30/2004 | US20040264278 Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data |
| 12/30/2004 | US20040264277 Sense amplifier driver and semiconductor device comprising the same |
| 12/30/2004 | US20040264276 Latch type sense amplifier method and apparatus |
| 12/30/2004 | US20040264275 Precharge apparatus in semiconductor memory device and precharge method using the same |
| 12/30/2004 | US20040264272 Method and apparatus for accelerating signal equalization between a pair of signal lines |
| 12/30/2004 | US20040264270 Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card |
| 12/30/2004 | US20040264269 Buffered memory module and method for testing same |
| 12/30/2004 | US20040264268 Erroneous operation preventing circuit of non-volatile memory device |
| 12/30/2004 | US20040264267 Signal transmitting system |
| 12/30/2004 | US20040264265 Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM |
| 12/30/2004 | US20040264262 Semiconductor memory preventing unauthorized copying |
| 12/30/2004 | US20040264261 Controller and method for writing data |
| 12/30/2004 | US20040264258 ROM embedded DRAM with bias sensing |
| 12/30/2004 | US20040264255 Memory device having data paths with multiple speeds |
| 12/30/2004 | US20040264251 Synchronous up/down address generator for burst mode read |
| 12/30/2004 | US20040264249 [dual reference cell sensing scheme for non-volatile memory] |
| 12/30/2004 | US20040264228 Small size ROM |
| 12/30/2004 | US20040264227 Semicondutor integrated circuit and electronic system |
| 12/30/2004 | US20040263366 Semiconductor integrated circuit |
| 12/30/2004 | US20040263229 Latch or phase detector device |
| 12/30/2004 | US20040263228 Apparatus for latency specific duty cycle correction |
| 12/30/2004 | US20040263117 Battery pack with built in communication port |
| 12/30/2004 | US20040262731 Self-testing printed circuit board comprising electrically programmable three-dimensional memory |
| 12/30/2004 | DE10323501A1 Schaltungsanordnung und Verfahren zur Einstellung einer Spannungsversorgung für einen Schreib-Lese-Verstärker eines integrierten Speichers Circuit arrangement and method for setting a power supply for a read-write amplifier of a built-in memory |
| 12/30/2004 | DE10323415A1 Data storage arrangement with control device and memory unit for computers and processors |
| 12/30/2004 | DE102004025975A1 Programming method for phase-change random access memory device, involves removing set pulse when memory device is determined to be in desired set state such that duration of set pulse is controlled based on state of memory device |
| 12/30/2004 | DE102004003357A1 Ferroelectric dynamic access memory cell array has reference voltage signal generator and calibration circuit for read out voltage |
| 12/29/2004 | WO2004114314A1 Information storage |
| 12/29/2004 | WO2004114312A2 Magnetic memory device on low-temperature substrate |
| 12/29/2004 | WO2004077439A3 An apparatus an method for a configurable mirror fast sense amplifier |
| 12/29/2004 | EP1492124A2 Three dimensional ferroelectric memory device. |
| 12/29/2004 | EP1492122A1 Methods and apparatus for memory sensing |
| 12/29/2004 | EP1492121A2 Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
| 12/29/2004 | EP1492120A2 Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |