| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 02/17/2005 | DE10210726B4 Latenz-Zeitschaltung für ein S-DRAM Latency time circuit for an S-DRAM |
| 02/17/2005 | DE102004035998A1 Schaltung und Verfahren zur Temperaturdetektion, Halbleiterbaustein und Auffrischsteuerverfahren Circuit and method for temperature detection, semiconductor device and Auffrischsteuerverfahren |
| 02/17/2005 | DE102004029032A1 Speichersystem Storage system |
| 02/17/2005 | DE102004011419A1 Speicherzellenfolgen in einem Widerstands-Kreuzungspunkt-Speicherzellarray Memory cell strings in a resistive cross-point memory cell array |
| 02/16/2005 | EP1068619B1 Semiconductor memory asynchronous pipeline |
| 02/16/2005 | EP0834134B1 Delay reduction in transfer of buffered data between two mutually asynchronous buses |
| 02/16/2005 | CN1582469A Digital audio device |
| 02/16/2005 | CN1581358A Memory and its driving method |
| 02/16/2005 | CN1581356A Storage device and method for amplifying voltage level of bit line and complementary bit line |
| 02/16/2005 | CN1581102A Circuit and method for implementing correction operation to only read memory in inlaid program |
| 02/16/2005 | CN1189890C Semiconductor memory device with multiple low-pissipation module type |
| 02/16/2005 | CN1189823C Data processing device, data processing method, terminal, transmission method for data processing device |
| 02/15/2005 | US6857042 Method for refreshing a dynamic memory |
| 02/15/2005 | US6857039 Bi-directional bus circuitry executing bi-directional data transmission while avoiding floating state |
| 02/15/2005 | US6856574 Semiconductor memory device |
| 02/15/2005 | US6856573 Column decoder configuration for a 1T/1C memory |
| 02/15/2005 | US6856571 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure |
| 02/15/2005 | US6856570 Apparatus for writing data bits to a memory array |
| 02/15/2005 | US6856569 Method and system for merging multiple fuse decompression serial bitstreams to support auxiliary fuseblow capability |
| 02/15/2005 | US6856567 Semiconductor device with self refresh test mode |
| 02/15/2005 | US6856566 Timer circuit and semiconductor memory incorporating the timer circuit |
| 02/15/2005 | US6856564 Noise resistant small signal sensing circuit for a memory device |
| 02/15/2005 | US6856563 Semiconductor memory device for enhancing bitline precharge time |
| 02/15/2005 | US6856559 Semiconductor memory device |
| 02/15/2005 | US6856558 Integrated circuit devices having high precision digital delay lines therein |
| 02/15/2005 | US6856557 Signal integrity checking circuit |
| 02/15/2005 | US6856547 Circuit for biasing an input node of a sense amplifier with a pre-charge stage |
| 02/15/2005 | US6856541 Segmented metal bitlines |
| 02/15/2005 | US6856532 Offset compensated sensing for magnetic random access memory |
| 02/15/2005 | US6856530 System and method to avoid voltage read errors in open digit line array dynamic random access memories |
| 02/15/2005 | US6856268 Control systems having an analog control unit that generates an analog value responsive to a digital value and having twice the resolution of the least significant bit of the digital value and methods of operating the same |
| 02/15/2005 | US6856030 Semiconductor latches and SRAM devices |
| 02/15/2005 | US6855574 Stress balanced semiconductor packages, method of fabrication and modified mold segment |
| 02/15/2005 | US6855564 Magnetic random access memory having transistor of vertical structure with writing line formed on an upper portion of the magnetic tunnel junction cell |
| 02/10/2005 | US20050034034 Control device with rewriteable control data |
| 02/10/2005 | US20050033908 Data storage device using SDRAM |
| 02/10/2005 | US20050033903 Integrated circuit device |
| 02/10/2005 | US20050033899 Semiconductor memory asynchronous pipeline |
| 02/10/2005 | US20050032313 Vertical gain cell |
| 02/10/2005 | US20050030824 Apparatus and method for controlling the access operation by a plurality of data processing devices to a memory |
| 02/10/2005 | US20050030820 Simultaneous bi-directional transceiver |
| 02/10/2005 | US20050030814 Data read circuit for use in a semiconductor memory and a method thereof |
| 02/10/2005 | US20050030809 Sensing circuit for a semiconductor memory |
| 02/10/2005 | US20050030808 Standby mode for use in a device having a multiple channel physical layer |
| 02/10/2005 | US20050030805 Memory device and method of amplifying voltage levels of bit line and complementary bit line |
| 02/10/2005 | US20050030802 Memory module including an integrated circuit device |
| 02/10/2005 | US20050030799 Logical data block, magnetic random access memory, memory module, computer system and method |
| 02/10/2005 | US20050030796 Circuit and/or method for implementing a patch mechanism for embedded program ROM |
| 02/10/2005 | US20050030783 Dynamic RAM and semiconductor device |
| 02/10/2005 | US20050030079 Delay circuits and related apparatus for extending delay time by active feedback elements |
| 02/10/2005 | US20050030064 Self-correcting i/o interface driver scheme for memory interface |
| 02/10/2005 | US20050029551 Semiconductor memory pipeline buffer |
| 02/10/2005 | DE10345550B3 Computer memory device with several random-access memory modules divided into disjunctive module groups each having memory cells organized in disjunctive cell groups with simultaneous write-in and read-out |
| 02/10/2005 | DE10330593A1 Integrated clock-pulse supply module for memory module, has phase control loop connected to clock signal input and generating second clock signal |
| 02/10/2005 | DE10329378B3 Dynamic random-access semiconductor memory for personal digital assistant or mobile telephone has memory sub-unit with memory cell and associated pre-charge equalize circuit switched via control circuit |
| 02/10/2005 | DE10329345A1 Vorrichtung und Verfahren zur Speicherung digitaler Daten Apparatus and method for storing digital data |
| 02/10/2005 | DE102004034934A1 Ausgabetreiber und Verfahren zum Reduzieren von Kopplungsrauschen Output driver and a method for reducing coupling noise |
| 02/10/2005 | DE102004027883A1 Integrierte Speicherschaltungsbausteine und Betriebsverfahren, die ausgeführt sind, um Datenbits mit einer niedrigeren Rate in einer Testbetriebsart auszugeben An integrated circuit memory devices and operating procedures that are designed to output data bits at a lower rate in a test mode |
| 02/10/2005 | DE102004014450A1 Measuring and compensating method of skews in dual in-line memory module, involves calculating relative skew of each data transmission line with respect to slowest data transmission line |
| 02/09/2005 | EP1505607A1 Asymmetric static random access memory device having reduced bit line leakage |
| 02/09/2005 | EP1505605A1 Improved sensing circuit for a semiconductor memory including bit line precharging and discharging functions |
| 02/09/2005 | EP1312183A4 Apparatus and method for operating a master-slave system with a clock signal and a separate phase signal |
| 02/09/2005 | CN2678014Y Recorder for send-out speech and music |
| 02/09/2005 | CN1578143A 半导体集成电路器件 The semiconductor integrated circuit device |
| 02/09/2005 | CN1577947A Precharge apparatus in semiconductor memory device and precharge method using the same |
| 02/09/2005 | CN1577846A Semicondutor integrated circuit and electronic system |
| 02/09/2005 | CN1577628A Semiconductor memory preventing unauthorized copying |
| 02/09/2005 | CN1577627A 半导体记忆模块 Semiconductor memory module |
| 02/09/2005 | CN1577626A Memory module integrated clock supply chip, module containing chip and operation of module |
| 02/09/2005 | CN1577625A Semiconductor storage device |
| 02/09/2005 | CN1577623A Data pass control device for masking write ringing in ddr sdram and method thereof |
| 02/09/2005 | CN1577622A Memory circuit, display device and electronic equipment each comprising the same |
| 02/09/2005 | CN1577620A 半导体存储装置 The semiconductor memory device |
| 02/09/2005 | CN1577613A Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data |
| 02/09/2005 | CN1577612A Semiconductor memory device and module for high frequency operation |
| 02/09/2005 | CN1577609A Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion |
| 02/09/2005 | CN1577608A Memory system having data inversion and data inversion method for a memory system |
| 02/09/2005 | CN1577607A Amplifying circuit, amplifying apparatus, and memory apparatus |
| 02/09/2005 | CN1577606A Sense amplifier driver and semiconductor device comprising the same |
| 02/09/2005 | CN1577255A Controller and method for writing data |
| 02/09/2005 | CN1577236A 存储系统 Storage Systems |
| 02/09/2005 | CN1577081A Layout method for miniaturized memory array area |
| 02/09/2005 | CN1188980C Data transmission method and system |
| 02/09/2005 | CN1188865C Method and device of using compressed data in far-end box to initialize integrated circuit |
| 02/09/2005 | CN1188864C Magnetic random access storage device |
| 02/09/2005 | CN1188863C Synchronous memory module with selective clock terminal joint and memory thereof |
| 02/08/2005 | US6854084 Partitioned random access memory |
| 02/08/2005 | US6854047 Data storage device and data transmission system using the same |
| 02/08/2005 | US6854041 DRAM-based separate I/O memory solution for communication applications |
| 02/08/2005 | US6854040 Non-volatile memory device with burst mode reading and corresponding reading method |
| 02/08/2005 | US6853602 Hiding error detecting/correcting latency in dynamic random access memory (DRAM) |
| 02/08/2005 | US6853601 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array |
| 02/08/2005 | US6853600 Ferro-electric random access memory using paraelectric and ferroelectric capacitor for generating a reference potential |
| 02/08/2005 | US6853599 Magnetic memory device implementing read operation tolerant to bitline clamp voltage (VREF) |
| 02/08/2005 | US6853594 Double data rate (DDR) data strobe receiver |
| 02/08/2005 | US6853593 Semiconductor memory device having over-driving scheme |
| 02/08/2005 | US6853591 Circuit and method for decreasing the required refresh rate of DRAM devices |
| 02/08/2005 | US6853590 Methods and apparatus for reading memory device register data |
| 02/08/2005 | US6853589 Clock phase adjustment method, integrated circuit, and method for designing the integrated circuit |
| 02/08/2005 | US6853588 First-in first-out memory circuit and method for executing same |