Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
03/2005
03/17/2005US20050060601 Apparatus and method for selectively configuring a memory device using a bi-stable relay
03/17/2005US20050060487 Memory device having a power down exit register
03/17/2005US20050060486 Dual buffer memory system for reducing data transmission time and control method thereof
03/17/2005US20050060482 Memory Interleave system
03/17/2005US20050058233 System and method for adaptive duty cycle optimization
03/17/2005US20050058012 Semiconductor memory device capable of accurate and stable operation
03/17/2005US20050058010 Addressing of memory matrix
03/17/2005US20050058002 Multi-port semiconductor memory
03/17/2005US20050057997 Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time
03/17/2005US20050057996 Semiconductor memory device for improving access time in burst mode
03/17/2005US20050057993 Semiconductor memory device
03/17/2005US20050057991 Data rewriting apparatus and data rewriting method
03/17/2005US20050057990 Read only memory devices with independently precharged virtual ground and bit lines
03/17/2005US20050057989 Synchronous dynamic random access memory
03/17/2005US20050057988 Method and device for testing semiconductor memory devices
03/17/2005US20050057987 Semiconductor device
03/17/2005US20050057984 Printed circuit card kit
03/17/2005US20050057983 Data output circuit in a semiconductor memory device and control method of a data output circuit
03/17/2005US20050057981 Semiconductor memory device capable of adjusting impedance of data output driver
03/17/2005US20050057980 Tri-state detection circuit for use in devices associated with an imaging system
03/17/2005US20050057978 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
03/17/2005US20050057977 Apparatus for tuning a RAS active time in a memory device
03/17/2005US20050057976 Low power consumption data input/output circuit of embedded memory device and data input/output method of the circuit
03/17/2005US20050057975 Metal programmable phase-locked loop
03/17/2005US20050057970 Nonvolatile memory device includng circuit formed of thin film transistors
03/17/2005US20050057961 Semiconductor memory device providing redundancy
03/17/2005US20050057955 Semiconductor integrated circuit device and information storage method therefor
03/17/2005US20050057953 Reading array cell with matched reference cell
03/17/2005US20050057572 Checkerboard buffer
03/17/2005US20050057281 Data output driver
03/17/2005US20050056876 Semiconductor memory device
03/17/2005US20050056866 Circuit arrays having cells with combinations of transistors and nanotube switching elements
03/17/2005US20050056825 Field effect devices having a drain controlled via a nanotube switching element
03/17/2005DE19848283B4 Halbleiterspeichereinrichtung mit verbessertem Treiber für den Leseverstärker A semiconductor memory device with improved sense amplifier driver for the
03/17/2005DE10338303A1 Steuerschaltung zur Steuerung der Flankensteilheit von Sendesignalen Control circuit for controlling the slew rate of transmitted signals
03/17/2005DE102004041023A1 Semiconductor integrated circuit device, has impedance controller to generate control codes that are variably related with impedance of external reference resistor, and termination circuit to terminate transfer line based on codes
03/17/2005DE102004041020A1 Reparaturvorrichtung und -verfahren und zugehöriger Halbleiterspeicherbaustein Repair apparatus and method and related semiconductor memory device
03/17/2005DE102004040962A1 Compensating circuit for semiconductor memory, has delay locked loop circuit which receives offset code from up-down counter, and generates pair of clock signals having different phase differences
03/17/2005DE102004039178A1 Memory control device for controlling reading or writing operation, has frequency change control device to deliver frequency change control signal to output based on multiple control signals and memory clock signal
03/17/2005DE102004032690A1 Halbleiterspeichervorrichtung, welche in der Lage ist, die Impedanz eines Datenausgangstreibers einzustellen A semiconductor memory device, which is able to adjust the impedance of a data output driver
03/17/2005DE102004031449A1 Gerät und Verfahren zum Kompensieren eines Phasenverzugs in einer Halbleiterspeichervorrichtung Apparatus and method for compensating for a phase delay in a semiconductor memory device
03/17/2005CA2537632A1 Low voltage operation dram control circuits
03/16/2005EP1515343A2 Semiconductor memory device
03/16/2005EP1514274A1 Memory storage device with heating element
03/16/2005EP1514273A1 Roll back method for a smart card
03/16/2005CN2686041Y Photo reader
03/16/2005CN2685983Y Card brusing bar code reading equipment
03/16/2005CN1596447A Cascode sense amp and column select circuit and method of operation
03/16/2005CN1595531A 半导体器件 Semiconductor devices
03/16/2005CN1595526A Portable test recording apparatus and method
03/16/2005CN1595397A Automatic making and playing method of audible text
03/16/2005CN1595373A A two-channel synchronous recording and storing method and equipment for fault recording data
03/16/2005CA2480841A1 Memory interleave system
03/15/2005US6868474 High performance cost optimized memory
03/15/2005US6868034 Circuits and methods for changing page length in a semiconductor memory device
03/15/2005US6868029 Semiconductor device with reduced current consumption in standby state
03/15/2005US6868025 Temperature compensated RRAM circuit
03/15/2005US6868024 Low voltage sense amplifier for operation under a reduced bit line bias voltage
03/15/2005US6868023 Semiconductor memory device based on dummy-cell method
03/15/2005US6868022 Redundant memory structure using bad bit pointers
03/15/2005US6868019 Reduced power redundancy address decoder and comparison circuit
03/15/2005US6868007 Semiconductor memory system with a data copying function and a data copy method for the same
03/15/2005US6867630 Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments
03/15/2005US6867626 Clock synchronization circuit having bidirectional delay circuit strings and controllable pre and post stage delay circuits connected thereto and semiconductor device manufactured thereof
03/15/2005CA2385422C Data reproduction apparatus and data storage medium
03/10/2005WO2005022542A1 Method and arrangement for the production of a memory chip having different data bit widths
03/10/2005WO2005022395A1 Circuit system and method for coupling a circuit module to or for decoupling same from a main bus
03/10/2005US20050055491 Method and apparatus for data inversion in memory device
03/10/2005US20050052944 Semiconductor integrated circuit device
03/10/2005US20050052943 Memory device and method of reading data from a memory device
03/10/2005US20050052941 Semiconductor memory
03/10/2005US20050052940 Readout circuit, solid state image pickup device using the same circuit, and camera system using the same
03/10/2005US20050052936 High speed power-gating technique for integrated circuit devices incorporating a sleep mode of operation
03/10/2005US20050052933 [device and method for breaking leakage current path]
03/10/2005US20050052931 Sense amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM)
03/10/2005US20050052927 Method and apparatus for assigning addresses to alarm system devices
03/10/2005US20050052925 Semiconductor memory device and semiconductor integrated circuit device
03/10/2005US20050052922 Flash memory device capable of reducing read time
03/10/2005US20050052921 Fast and economical establishment of remote copy
03/10/2005US20050052920 Time slot memory management
03/10/2005US20050052917 Column read amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM)
03/10/2005US20050052916 Semiconductor memory
03/10/2005US20050052915 Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
03/10/2005US20050052913 Semi-conductor memory component, and a process for operating a semi-conductor memory component
03/10/2005US20050052912 Circuit and system for addressing memory modules
03/10/2005US20050052910 Delay locked loop "ACTIVE COMMAND" reactor
03/10/2005US20050052909 Semiconductor memory device
03/10/2005US20050052897 Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing
03/10/2005US20050052896 Nonvolatile ferroelectric memory device having multi-bit control function
03/10/2005US20050052892 Systems for programmable memory using silicided poly-silicon fuses
03/10/2005US20050052218 Fuse latch circuit with non-disruptive re-interrogation
03/10/2005US20050051887 Clock distribution networks and conductive lines in semiconductor integrated circuits
03/09/2005EP1513161A2 Semiconductor memory device
03/09/2005EP1513157A1 Method for multibank memory scheduling
03/09/2005EP1513072A2 Method for multibank memory scheduling
03/09/2005EP1512982A2 Sensing devices and sensing circuits
03/09/2005EP1512079A2 Pseudo multiport data memory has stall facility
03/09/2005EP1316090B1 Non-volatile passive matrix and method for readout of the same
03/09/2005CN1591692A 半导体存储装置 The semiconductor memory device
03/09/2005CN1591690A 半导体集成电路装置和ic卡 The semiconductor integrated circuit device and ic card
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