| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 03/02/2006 | US20060044887 Power efficient memory and cards |
| 03/02/2006 | US20060044881 Unified multilevel cell memory |
| 03/02/2006 | US20060044880 Multiple-level data compression read more for memory testing |
| 03/02/2006 | US20060044879 Semiconductor memory device |
| 03/02/2006 | US20060044878 Programming of programmable resistive memory devices |
| 03/02/2006 | DE19518953B4 Datenbusleitungsleseverstärkungseinrichtung Datenbusleitungsleseverstärkungseinrichtung |
| 03/02/2006 | DE10300026B4 Softwaregesteuertes System zur Konfiguration von Zugriffs-Steuermodi eines DRAM-Modul-Sockels Software-controlled system for configuring access control modes of a DRAM module socket |
| 03/02/2006 | DE10231954B4 Schaltungsbaustein mit Zeitsteuerung Mounted module timing |
| 03/02/2006 | DE102005037072A1 Dynamische Anpassung von Signalpfad und Referenzpfad zur Messung Dynamic adjustment of the signal path and reference path for measuring |
| 03/02/2006 | DE102004013115B4 Schaltung zum Formen eines Kommunikationssignals und damit versehene Speichereinheit Circuitry for forming a communication signal and thus provided storage unit |
| 03/01/2006 | EP1630815A1 Memory circuit with supply voltage flexibility and supply voltage adapted performance |
| 03/01/2006 | EP1630814A1 Method for reading electrically programmable and erasable memory cells with anticipated bit line precharge |
| 03/01/2006 | EP1629503A1 Intergrated charge sensing scheme for resistive memories |
| 03/01/2006 | CN1742341A Hardware security device for magnetic memory cells |
| 03/01/2006 | CN1741194A Nonvolatile semiconductor memory device and read method |
| 03/01/2006 | CN1741192A Data write circuit and data write method for semiconductor storage device |
| 03/01/2006 | CN1741191A Multiport memory |
| 03/01/2006 | CN1741189A Multi-tone audio-information playing method and apparatus |
| 03/01/2006 | CN1741188A Asynchronous data clock domain conversion |
| 03/01/2006 | CN1741187A Integrated circuit device providing selectively variable write latency and method thereof |
| 02/28/2006 | USRE38997 Information storage and information processing system utilizing state-designating member provided on supporting card surface which produces write-permitting or write-inhibiting signal |
| 02/28/2006 | US7007140 Storage device, storage device controlling method, and program |
| 02/28/2006 | US7006403 Self timed bit and read/write pulse stretchers |
| 02/28/2006 | US7006402 Multi-port memory device |
| 02/28/2006 | US7006401 Semiconductor storage device and refresh control method thereof |
| 02/28/2006 | US7006400 Content addressable memory with reduced instantaneous current and power consumption during a search |
| 02/28/2006 | US7006397 Data write circuit in memory system and data write method |
| 02/28/2006 | US7006396 Semiconductor memory device and precharge control method |
| 02/28/2006 | US7006394 Apparatus and method for semiconductor device repair with reduced number of programmable elements |
| 02/28/2006 | US7006393 Method and apparatus for semiconductor device repair with reduced number of programmable elements |
| 02/28/2006 | US7006392 Memory redundancy programming |
| 02/28/2006 | US7006391 Semiconductor memory device allowing increase in capacity and operation speed with a suppressed layout area |
| 02/28/2006 | US7006389 Voltage translator for multiple voltage operations |
| 02/28/2006 | US7006388 Memory with reference-initiated sequential sensing |
| 02/28/2006 | US7006387 Semiconductor memory device with adjustable I/O bandwidth |
| 02/28/2006 | US7006386 Storage device employing a flash memory |
| 02/28/2006 | US7006380 Non-volatile semiconductor memory device reading and writing multi-value data from and into pair-cell |
| 02/28/2006 | US7006369 Design and use of a spacer cell to support reconfigurable memories |
| 02/28/2006 | US7006341 Multichip module and multichip shutdown method |
| 02/28/2006 | US7006025 Method for generating a reference current for sense amplifiers and corresponding generator |
| 02/28/2006 | US7005906 Semiconductor integrated-circuit device and method to speed-up CMOS circuit |
| 02/28/2006 | US7005897 Output circuit |
| 02/28/2006 | US7005892 Circuit technique for high speed low power data transfer bus |
| 02/28/2006 | US7005890 Device for generating a bit line selection signal of a memory device |
| 02/28/2006 | US7004759 Modules having a plurality of contacts along edges thereof configured to conduct signals to the modules and further having a plurality of contacts along edges thereof configured to conduct signals from the modules |
| 02/23/2006 | WO2006019624A2 Method and system for controlling refresh to avoid memory cell data losses |
| 02/23/2006 | WO2006019466A2 Memory with fault tolerant reference circuitry |
| 02/23/2006 | US20060041822 Error correction in ROM embedded DRAM |
| 02/23/2006 | US20060041711 Memory module, memory system, and information device |
| 02/23/2006 | US20060041704 Dual port memory with asymmetric inputs and outputs, device, system and method |
| 02/23/2006 | US20060039227 Memory device having staggered memory operations |
| 02/23/2006 | US20060039223 Semiconductor memory device, control method thereof, and control method semiconductor device |
| 02/23/2006 | US20060039222 Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages |
| 02/23/2006 | US20060039221 Memory card, memory card control method and memory card access control method |
| 02/23/2006 | US20060039220 Semiconductor memory device, test circuit and test method |
| 02/23/2006 | US20060039219 Replenishment for internal voltage |
| 02/23/2006 | US20060039218 Semiconductor device |
| 02/23/2006 | US20060039217 Power efficient read circuit for a serial output memory device and method |
| 02/23/2006 | US20060039216 Integrated circuit memory device with bit line pre-charging based upon partial address decording |
| 02/23/2006 | US20060039215 Memory with fault tolerant reference circuitry |
| 02/23/2006 | US20060039214 Driving circuit, driving method of electro-optical device, electro-optical device, and electronic apparatus |
| 02/23/2006 | US20060039213 Integrated circuit I/O using a high performance bus interface |
| 02/23/2006 | US20060039212 Method and test structure for evaluating threshold voltage distribution in a memory array |
| 02/23/2006 | US20060039211 Method and apparatus for enabling a user to determine whether a defective location in a memory device has been remapped to a redundant memory portion |
| 02/23/2006 | US20060039209 Semiconductor memory |
| 02/23/2006 | US20060039208 Metal-poly integrated capacitor structure |
| 02/23/2006 | US20060039207 Self-adaptive program delay circuitry for programmable memories |
| 02/23/2006 | US20060039206 Semiconductor device including voltage level conversion output circuit |
| 02/23/2006 | US20060039205 Reducing the number of power and ground pins required to drive address signals to memory modules |
| 02/23/2006 | US20060039204 Method and apparatus for encoding memory control signals to reduce pin count |
| 02/23/2006 | US20060039203 Register file apparatus and method incorporating read-after-write blocking using detection cells |
| 02/23/2006 | US20060039202 Register file method incorporating read-after-write blocking using detection cells |
| 02/23/2006 | US20060039201 Sequential access memory with system and method |
| 02/23/2006 | US20060039200 Non-volatile memory cell, fabrication method and operating method thereof |
| 02/23/2006 | US20060039191 System and method for reading a memory cell |
| 02/23/2006 | US20060039178 Device having a memory array storing each bit in multiple memory cells |
| 02/23/2006 | US20060038168 Terahertz interconnect system and applications |
| 02/23/2006 | DE102004039422A1 Data memory arrangement, has access unit coupled with data output of addressing unit and designed for cyclic access on registers, where unit is designed for selection of memories and transmission of contents of data word |
| 02/23/2006 | DE102004006288B4 Integrierter Halbleiterspeicher mit redundanten Speicherzellen sowie Verfahren zum Testen eines integrierten Halbleiterspeichers mit redundanten Speicherzellen und Verfahren zum Betreiben eines integrierten Halbleiterspeichers mit redundanten Speicherzellen Integrated semiconductor memory with redundant memory cells as well as methods for testing an integrated semiconductor memory with redundant memory cells and methods for operating an integrated semiconductor memory with redundant memory cells |
| 02/23/2006 | CA2577272A1 Register file apparatus and method incorporating read-after-write blocking using detection cells |
| 02/22/2006 | EP1627392A1 Circuit configuration for a current switch of a bit/word line of a mram device |
| 02/22/2006 | EP1627266A1 Floating-gate reference circuit |
| 02/22/2006 | EP0946988B1 Memory redundancy circuit using single polysilicon floating gate transistors as redundancy elements |
| 02/22/2006 | CN2760712Y Earphone type playing device |
| 02/22/2006 | CN1737943A 存储器接口和数据处理系统 Memory interface and a data processing system |
| 02/21/2006 | US7003684 Memory control chip, control method and control circuit |
| 02/21/2006 | US7003619 Memory device and method for storing and reading a file system structure in a write-once memory array |
| 02/21/2006 | US7003618 System featuring memory modules that include an integrated circuit buffer devices |
| 02/21/2006 | US7002873 Memory array with staged output |
| 02/21/2006 | US7002872 Semiconductor memory device with a decoupling capacitor |
| 02/21/2006 | US7002870 Speeding up the power-up procedure for low power RAM |
| 02/21/2006 | US7002869 Voltage regulator circuit |
| 02/21/2006 | US7002868 High-speed, two-port dynamic random access memory (DRAM) with a late-write configuration |
| 02/21/2006 | US7002867 Refresh control circuit for ICs with a memory array |
| 02/21/2006 | US7002866 Semiconductor memory device |
| 02/21/2006 | US7002865 Nonvolatile semiconductor memory device |
| 02/21/2006 | US7002864 SRAM-compatible memory device having three sense amplifiers between two memory blocks |
| 02/21/2006 | US7002863 Driving a DRAM sense amplifier having low threshold voltage PMOS transistors |
| 02/21/2006 | US7002862 Semiconductor memory device with sense amplifier driver having multiplied output lines |
| 02/21/2006 | US7002861 Memory device for controlling programming setup time |