Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
02/2007
02/01/2007US20070025170 Differential and hierarchical sensing for memory circuits
02/01/2007US20070025169 Memory array with a delayed wordline boost
02/01/2007US20070025165 Charge pump for programmable semiconductor memory
02/01/2007US20070025164 Voltage generating circuit, semiconductor memory device comprising the same, and voltage generating method
02/01/2007US20070025161 3-level non-volatile semiconductor memory device and method of driving the same
02/01/2007US20070025149 Nonvolatile Semiconductor Memory Device
02/01/2007US20070025141 SRAM, semiconductor memory device, and method for maintaining data in SRAM
02/01/2007US20070025133 System and method for optical interconnecting memory devices
02/01/2007US20070024344 Semiconductor integrated circuit
02/01/2007US20070022601 Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices
02/01/2007DE69932962T2 Kodierungsverfahren und Speicheranordnung Coding method and storage device
02/01/2007DE19952947B4 Anordnung zum Auslesen von Register-Information Arrangement for reading register information
02/01/2007DE112005000353T5 Komplementäre Lateral-Nitrid-Trasistoren Complementary Lateral nitride Trasistoren
02/01/2007DE102006034498A1 Karte mit integriertem Schaltkreis und Verfahren zum Verbessern der Schreib-/Leselebensdauer von nicht-flüchtigem Speicher An integrated circuit and method for improving the read / write life of non-volatile memory
02/01/2007DE102006033385A1 Speicherbauelement und Verfahren zum Ansteuern einer Wortleitung für einen Datenlesevorgang Memory device and method for driving a word line for a data read operation
02/01/2007DE102006032327A1 Halbleiterspeichermodul und -System A semiconductor memory module and system
02/01/2007DE102006031055A1 Halbleiterspeichervorrichtung und Verfahren zu deren Herstellung A semiconductor memory device and methods for their preparation
02/01/2007DE102006020773A1 Halbleiterspeicherbauelement und zugehöriges Latenzsignalerzeugungsverfahren The semiconductor memory device and associated latency signal generating method
02/01/2007DE102005036528A1 Speicherbaustein und Verfahren zum Betreiben eines Speicherbausteins Memory device and method of operating a memory device
02/01/2007DE102005035661A1 Halbleiter-Speicherbauelement-System, und Verfahren zum Betreiben eines Halbleiter-Speicherbauelement-Systems A semiconductor memory device system, and method of operating a semiconductor memory device system
02/01/2007DE102005031643A1 DRAM-Speicher DRAM memory
01/2007
01/31/2007EP1748444A1 Security method and system for an integrated circuit, particularly a memory
01/31/2007CN2864905Y Digital language-studying machine
01/31/2007CN1906697A Method for operating a data storage apparatus employing passive matrix addressing
01/31/2007CN1906696A Internal voltage reference for memory interface
01/31/2007CN1905073A Semiconductor memory card and data reading apparatus
01/31/2007CN1905065A Impedance adjusting circuit and method
01/31/2007CN1905062A 铁电存储装置 Ferroelectric memory device
01/31/2007CN1905059A Multi-port memory based on DRAM core
01/31/2007CN1905058A 半导体器件 Semiconductor devices
01/31/2007CN1905057A 存储器 Memory
01/31/2007CN1904981A Display driver circuit
01/31/2007CN1904854A Stream data buffer unit and access method thereof
01/30/2007US7171607 Apparatus and method for verifying erasure correction function
01/30/2007US7171597 Input/output compression test circuit
01/30/2007US7171574 DDR clocking
01/30/2007US7171536 Unusable block management within a non-volatile memory system
01/30/2007US7171528 Method and apparatus for generating a write mask key
01/30/2007US7170828 Removable face plate compressed digital music player
01/30/2007US7170819 Integrated semiconductor memory device for synchronizing a signal with a clock signal
01/30/2007US7170818 Semiconductor memory device and module for high frequency operation
01/30/2007US7170817 Access of two synchronous busses with asynchronous clocks to a synchronous single port ram
01/30/2007US7170815 Memory apparatus having multi-port architecture for supporting multi processor
01/30/2007US7170814 Multi-port semiconductor memory
01/30/2007US7170813 Memory circuit receivers activated by enable circuit
01/30/2007US7170807 Data storage device and refreshing method for use with such device
01/30/2007US7170806 Data path having grounded precharge operation and test compression capability
01/30/2007US7170805 Memory devices having bit line precharge circuits with off current precharge control and associated bit line precharge methods
01/30/2007US7170802 Flexible and area efficient column redundancy for non-volatile memories
01/30/2007US7170801 Method for replacing defects in a memory and apparatus thereof
01/30/2007US7170800 Low-power delay buffer circuit
01/30/2007US7170799 SRAM and dual single ended bit sense for an SRAM
01/30/2007US7170797 Test data topology write to memory using latched sense amplifier data and row address scrambling
01/30/2007US7170790 Sensing circuit
01/30/2007US7170789 Semiconductor storage device and electronic equipment
01/30/2007US7170777 Phase change memory device and method of operating the same
01/30/2007US7170776 Non-volatile memory device conducting comparison operation
01/30/2007US7170771 Method of reading a data bit including detecting conductivity of a volume of alloy exposed to an electron beam
01/30/2007US7170325 Circuit for controlling a delay time of input pulse and method of controlling the same
01/30/2007US7170313 Apparatus for calibrating termination voltage of on-die termination
01/30/2007US7170124 Trench buried bit line memory devices and methods thereof
01/30/2007US7170114 Semiconductor device
01/30/2007US7170091 Probe look ahead: testing parts not currently under a probehead
01/30/2007US7169624 Shared bit line cross-point memory array manufacturing method
01/25/2007WO2007010115A1 Reading amplifier for non-volatile memory
01/25/2007US20070022478 Information processing apparatus and method of ensuring security thereof
01/25/2007US20070022260 Data processor memory circuit
01/25/2007US20070020859 Method of making non-volatile field effect devices and arrays of same
01/25/2007US20070019491 Refresh control circuit and method for performing a repetition refresh operation and semiconductor memory device having the same
01/25/2007US20070019489 Disabling clocked standby mode based on device temperature
01/25/2007US20070019488 Temperature update masking to ensure correct measurement of temperature when references become unstable
01/25/2007US20070019487 Reference current generator
01/25/2007US20070019486 High speed array pipeline architecture
01/25/2007US20070019485 Semiconductor memory
01/25/2007US20070019484 Memory device and method for improving speed at which data is read from non-volatile memory
01/25/2007US20070019483 Redundancy selector circuit for use in non-volatile memory device
01/25/2007US20070019482 Method for detecting data strobe signal
01/25/2007US20070019481 Semiconductor memories with block-dedicated programmable latency register
01/25/2007US20070019480 Test circuitry and testing methods
01/25/2007US20070019479 Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions
01/25/2007US20070019467 Semiconductor memory device
01/25/2007US20070018157 Methods of forming phase change storage cells for memory devices
01/25/2007DE202006016441U1 Image and tone display and playback system for use in TV set with remote control, uses remote control of TV set as interface between remote control and TV set, and as reading unit for selecting images and tones from external storage medium
01/25/2007DE102006032948A1 Integrierte Empfängerschaltung Integrated receiver circuit
01/25/2007DE102006032438A1 Halbleiterspeichervorrichtung mit verbundenen Bitleitungen sowie Datenverschiebeverfahren hierfür A semiconductor memory device with bit lines and associated data shifting method therefor
01/25/2007DE102006024434A1 Integrierter Schaltungschip mit einer über eine zweite Verzögerungsschaltung abgeglichenen ersten Verzögerungsschaltung und Verfahren zum Einstellen einer Verzögerungszeit Integrated circuit chip having a balanced via a second delay circuit said first delay circuit and method for adjusting a delay time
01/25/2007DE102005045952B3 Bit line voltage supplying method for e.g. random access memory, involves loading bit line with output potential and providing charging devices that are activated and deactivated based on potential of virtual voltage supply line
01/25/2007DE102005032313A1 Verfahren zur Speicherverwaltung bei der Ausführung einer Anwendung durch einen tragbaren Datenträger Memory management method in the execution of an application by a portable data carrier
01/24/2007EP1746513A2 Architecture for a universal serial bus-based PC flash disk
01/24/2007EP1746491A1 Method for accessing data, apparatus and recording medium for performing that method
01/24/2007EP1745487A2 Charge pump clock for non-volatile memories
01/24/2007EP1745486A1 Multiple data rate ram memory controller
01/24/2007EP1745377A2 Error correction in an electronic circuit
01/24/2007EP1535162A4 Memory device supporting a dynamically configurable core organisation
01/24/2007CN2862265Y Audio control MP3 player
01/24/2007CN2860848Y Digital business card
01/24/2007CN1902713A Flexible and area efficient column redundancy for non-volatile memories
01/24/2007CN1902708A Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
01/24/2007CN1901091A Page buffer circuit and methods for reading and programming data with the same
01/24/2007CN1901090A Storage and reproduction apparatus