Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
02/2007
02/22/2007US20070040200 Trench buried bit line memory devices and methods thereof
02/22/2007DE102006039436A1 Speicherbauelement Memory device
02/22/2007DE102006034495A1 Verfahren zum Durchführen einer Programmieroperation eines nicht-flüchtigen Speicherbauelements und nicht-flüchtigen Speicherbauelement A method for performing a programming operation of a nonvolatile memory device and non-volatile memory device
02/22/2007DE102006031575A1 Page buffer for non-volatile memory device, e.g. flash memory, has shared sense circuit that joins latch input node to reference potential in response to voltages at sense node and at other cache latch node
02/22/2007DE102006029287A1 DRAM-Chipbaustein kommunizierend mit Flash-Speicherchip und einen solchen Baustein umfassender Mehrchip-Verbund DRAM chip module communicating with flash memory chip and a comprehensive multi-chip module such composite
02/22/2007DE102006028683A1 Parallele Datenpfadarchitektur Parallel data path architecture
02/22/2007DE102006022124A1 Eingangsschaltung mit aktualisiertem Ausgangssignal, das mit Taktsignal synchronisiert ist With updated input circuit output signal which is synchronized with clock signal
02/22/2007DE102004053602B4 Speichersystem und Verfahren zur Steuerung eines Speicherbauelements, um verschiedenartige Charakteristika auf ein und demselben Speicherbauelement zu erzielen Storage system and method for controlling a memory device in order to achieve various characteristics in the same memory device
02/22/2007DE10131708B4 Integrierte Schaltung zum Empfang eines Taktsignals, insbesondere für eine Halbleiterspeicherschaltung An integrated circuit for receiving a clock signal, in particular for a semiconductor memory circuit
02/21/2007EP1754229A2 System and method for improving performance in computer memory systems supporting multiple memory access latencies
02/21/2007EP1754131A2 Throttling memory in a computer system
02/21/2007EP1623432A4 Semiconductor memory cell, array, architecture and device, and method of operating same
02/21/2007EP1620859A4 Reference current generator, and method of programming, adjusting and/or operating same
02/21/2007CN2872546Y Controller of broadcasting device
02/21/2007CN2872545Y Portable loundspeaker system of U-disk MP3
02/21/2007CN2872469Y Presetting device of electrical appliance
02/21/2007CN1918842A Content distribution systems and methods
02/21/2007CN1918661A Secured phase-change devices
02/21/2007CN1918660A Memory device with several random-access memory chip
02/21/2007CN1917081A 半导体存储器件 A semiconductor memory device
02/21/2007CN1917080A Safe U disc storage system and method
02/21/2007CN1917079A Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory
02/21/2007CN1301592C Circuit of regenerating resetting and clock signals and method thereof and corresponding high-speed digital system
02/20/2007US7181721 Short edge management in rule based OPC
02/20/2007US7181650 Fault tolerant data storage circuit
02/20/2007US7181638 Method and apparatus for skewing data with respect to command on a DDR interface
02/20/2007US7181579 Integrated memory having redundant units of memory cells and method for testing an integrated memory
02/20/2007US7181566 Scratch control memory array in a flash memory device
02/20/2007US7180824 Semiconductor memory device with a page mode
02/20/2007US7180822 Semiconductor memory device without decreasing performance thereof even if refresh operation or word line changing operation occur during burst operation
02/20/2007US7180815 Semiconductor integrated circuit device
02/20/2007US7180814 Low power circuits with small voltage swing transmission, voltage regeneration and wide bandwidth architecture
02/20/2007US7180811 Semiconductor memory device informing internal voltage level using ready/busy pin
02/20/2007US7180810 Method of breaking down a fuse in a semiconductor device
02/20/2007US7180809 Refresh control circuit of pseudo SRAM
02/20/2007US7180808 Semiconductor memory device for performing refresh operation
02/20/2007US7180807 Semiconductor memory device having a delay circuit
02/20/2007US7180806 Memory device, refresh control circuit to be used for the memory device, and refresh method
02/20/2007US7180805 Differental current source for generating DRAM refresh signal
02/20/2007US7180804 High performance sense amplifier and method thereof for memory system
02/20/2007US7180803 Data compression read mode for memory testing
02/20/2007US7180802 Method of stress-testing an isolation gate in a dynamic random access memory
02/20/2007US7180801 Memory circuit with shared redundancy
02/20/2007US7180800 Interface circuit for adaptively latching data input/output signal by monitoring data strobe signal and memory system including the interface circuit
02/20/2007US7180799 Circuit for setting one of a plurality of organization forms of an integrated circuit and method for operating it
02/20/2007US7180798 Semiconductor physical quantity sensing device
02/20/2007US7180797 Reduced power registered memory module and method
02/20/2007US7180794 Oscillating circuit, booster circuit, nonvolatile memory device, and semiconductor device
02/20/2007US7180793 Semiconductor non-volatile storage device
02/20/2007US7180792 Efficient latch array initialization
02/20/2007US7180791 Flash with consistent latency for read operations
02/20/2007US7180790 Non-volatile memory device having controlled bulk voltage and method of programming same
02/20/2007US7180780 Multi-level-cell programming methods of non-volatile memories
02/20/2007US7180771 Device and method for pulse width control in a phase change memory device
02/20/2007US7180765 Ferroelectric memory
02/20/2007US7180327 Memory module system with efficient control of on-die termination
02/20/2007US7180278 Real current sense apparatus for a DC-to-DC converter
02/20/2007US7180211 Temperature sensor
02/20/2007US7179690 High reliability triple redundant latch with voting logic on each storage node
02/15/2007WO2007019041A1 Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals
02/15/2007US20070038906 Column/row redundancy architecture using latches programmed from a look up table
02/15/2007US20070038803 Transparent SDRAM in an embedded environment
02/15/2007US20070038320 Portable sound reproducing system and method
02/15/2007US20070038319 Portable sound reproducing system and method
02/15/2007US20070036023 Method for detecting data strobe signal
02/15/2007US20070036017 Semiconductor memory device and a refresh clock signal generator thereof
02/15/2007US20070036015 Semiconductor device temperature sensor and semiconductor storage device
02/15/2007US20070036014 Nonvolatile memory device with multiple references and corresponding control method
02/15/2007US20070036013 Semiconductor memory with wordline timing
02/15/2007US20070036012 Stable source-coupled sense amplifier
02/15/2007US20070036011 Shared redundant memory architecture and memory system incorporating same
02/15/2007US20070036009 Semiconductor memory devices and methods for generating column enable signals thereof
02/15/2007US20070036006 System and method for mode register control of data bus operating mode and impedance
02/15/2007US20070036005 Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory
02/15/2007US20070036004 Hybrid non-volatile memory device
02/15/2007US20070035988 SRAM, semiconductor memory device, method for maintaining data in SRAM, and electronic device
02/15/2007US20070035980 System and method for optically interconnecting memory devices
02/15/2007US20070035336 Clock generating circuit with multiple modes of operation
02/15/2007DE20023887U1 Architektur für eine USB-basierte PC-Flashspeichervorrichtung Architecture for a USB-based PC flash memory device
02/15/2007DE19963417B4 Nichtflüchtiger ferroelektrischer Speicher Non-volatile ferroelectric memory
02/15/2007DE102006029477A1 Zweifrequenz-Zuerst-Hinein-Zuerst-Hinaus-Struktur Two-frequency first-in-first-out structure
02/15/2007DE102006028966A1 Phasenregelkreisschaltung, Verfahren zum Verriegeln der Phase, Speicherbauelement und Speichersystem Phase-locked loop circuit for locking the phase method, memory device and memory system
02/15/2007DE102006024096A1 Verzögerungsregelkreis Delay locked loop
02/15/2007DE102005050811B3 Dynamic random access memory-semiconductor memory device, has two memory cells with gates, where gates are switchable by control switching device at beginning of preloading process for loading bit lines to compensation voltage
02/14/2007EP1751869A1 Clock capture in clock synchronization circuitry
02/14/2007EP1751763A2 Systems and methods for write protection of non-volatile memory devices
02/14/2007EP1751762A2 Automatic hidden refresh in a dram and method therefor
02/14/2007EP1751545A2 Measuring device and methods for use therewith
02/14/2007EP1634296A4 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
02/14/2007CN2869990Y Dats storing apparatus with cipher read-write protection
02/14/2007CN2869916Y Glasses type vintual MP4 muti-media playing device
02/14/2007CN1914690A Integrated circuit device with a ROM matrix
02/14/2007CN1914689A Non-volatile memory and method with control data management
02/14/2007CN1913758A Portable multimedia device with display bracket switch and method of operating the same
02/14/2007CN1913384A Audio source play system utilizing head-on earphone and audio-source play method
02/14/2007CN1300851C Semiconductor memory device with signal distributive circuits formed above memory unit
02/14/2007CN1300803C Method for driving remapping in flash memory and its flash memory system structure
02/14/2007CN1300802C Semiconductor storing device
02/14/2007CN1300801C Automatic partial-array updating system and method for semiconductor memory
02/13/2007US7178088 Method and circuit for error correction, error correction encoding, data reproduction, or data recording