| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 02/13/2007 | US7178048 System and method for signal synchronization based on plural clock signals |
| 02/13/2007 | US7178039 Method and arrangement for the verification of NV fuses as well as a corresponding computer program product and a corresponding computer-readable storage medium |
| 02/13/2007 | US7178012 Semiconductor device |
| 02/13/2007 | US7178001 Semiconductor memory asynchronous pipeline |
| 02/13/2007 | US7177999 Reading extended data burst from memory |
| 02/13/2007 | US7177974 Data processing device with a memory location in which data is stored according to a WOM (write once memory) code |
| 02/13/2007 | US7177231 Selectable clock input |
| 02/13/2007 | US7177229 Apparatus for tuning a RAS active time in a memory device |
| 02/13/2007 | US7177228 Apparatus and method for controlling enable time of signal controlling operation of data buses of memory device |
| 02/13/2007 | US7177227 Transistor layout configuration for tight-pitched memory array lines |
| 02/13/2007 | US7177225 Block redundancy implementation in heirarchical RAM'S |
| 02/13/2007 | US7177223 Memory device and method having banks of different sizes |
| 02/13/2007 | US7177222 Reducing power consumption in a data storage system |
| 02/13/2007 | US7177220 Refresh counter with dynamic tracking of process, voltage and temperature variation for semiconductor memory |
| 02/13/2007 | US7177219 Disabling clocked standby mode based on device temperature |
| 02/13/2007 | US7177218 DRAM device with a refresh period that varies responsive to a temperature signal having a hysteresis characteristic |
| 02/13/2007 | US7177217 Method and circuit for verifying and eventually substituting defective reference cells of a memory |
| 02/13/2007 | US7177216 Twin-cell bit line sensing configuration |
| 02/13/2007 | US7177215 Semiconductor memory device operating at high speed and low power consumption |
| 02/13/2007 | US7177214 Methods and systems for dynamically selecting word line off times and/or bit line equalization start times in memory devices |
| 02/13/2007 | US7177213 Capacitor supported precharging of memory digit lines |
| 02/13/2007 | US7177212 Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase |
| 02/13/2007 | US7177211 Memory channel test fixture and method |
| 02/13/2007 | US7177209 Semiconductor memory device and method of driving the same |
| 02/13/2007 | US7177208 Circuit and method for operating a delay-lock loop in a power saving manner |
| 02/13/2007 | US7177207 Sense amplifier timing |
| 02/13/2007 | US7177206 Power supply circuit for delay locked loop and its method |
| 02/13/2007 | US7177204 Pulse width adjusting circuit for use in semiconductor memory device and method therefor |
| 02/13/2007 | US7177203 Data readout circuit and semiconductor device having the same |
| 02/13/2007 | US7177202 Method for accessing a single port memory |
| 02/13/2007 | US7177201 Negative bias temperature instability (NBTI) preconditioning of matched devices |
| 02/13/2007 | US7177196 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells |
| 02/13/2007 | US7177195 Reducing the effects of noise in non-volatile memories through multiple reads |
| 02/13/2007 | US7177182 Rewriteable electronic fuses |
| 02/13/2007 | US7177181 Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics |
| 02/13/2007 | US7177176 Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength |
| 02/13/2007 | US7177171 Semiconductor device |
| 02/13/2007 | US7177170 Apparatus and method for selectively configuring a memory device using a bi-stable relay |
| 02/13/2007 | US7176729 Semiconductor integrated circuit controlling output impedance and slew rate |
| 02/13/2007 | US7176711 On-die termination impedance calibration device |
| 02/13/2007 | US7176655 Battery pack with built in communication port |
| 02/13/2007 | CA2429366C A method for non-destructive readout and apparatus for use with the method |
| 02/08/2007 | WO2006130763A3 Partial page scheme for memory technologies |
| 02/08/2007 | WO2005034189A3 Integrated circuit power management for reducing leakage current in circuit arrays and method therefor |
| 02/08/2007 | US20070033379 Active memory processing array topography and method |
| 02/08/2007 | US20070030756 Charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same |
| 02/08/2007 | US20070030752 Programmable strength output buffer for RDIMM address register |
| 02/08/2007 | US20070030751 Semiconductor memory having a short effective word line cycle time and method for reading data from a semiconductor memory of this type |
| 02/08/2007 | US20070030749 Voltage down converter for high speed memory |
| 02/08/2007 | US20070030748 Bit line sense amplifier and method thereof |
| 02/08/2007 | US20070030747 Data recording device |
| 02/08/2007 | US20070030746 Memory device testing to support address-differentiated refresh rates |
| 02/08/2007 | US20070030745 Referencing scheme for trap memory |
| 02/08/2007 | US20070030744 Semiconductor memory device |
| 02/08/2007 | US20070030741 Semiconductor memory device |
| 02/08/2007 | US20070030739 Method of comparison between cache and data register for non-volatile memory |
| 02/08/2007 | US20070030738 Technique to suppress leakage current |
| 02/08/2007 | US20070030028 Programmable array logic circuit employing non-volatile ferromagnetic memory cells |
| 02/08/2007 | US20070029544 Interconnected high speed electron tunneling devices |
| 02/08/2007 | DE19513587B4 Speicherbauelement und Verfahren zum Programmieren eines Steuerbetriebsmerkmals eines Speicherbauelements Memory device and method for programming a control operation characteristic of a memory device |
| 02/08/2007 | DE102004052868B4 Integrierte Schaltkreis-Anordnung und Schaltkreis-Array Integrated circuit arrangement and circuit array |
| 02/07/2007 | EP1750276A1 Semiconductor device |
| 02/07/2007 | EP1750274A1 Magnetic memory device |
| 02/07/2007 | EP1750273A1 Memory cell with increased access reliability |
| 02/07/2007 | EP1749634A1 Molded body of thermoplastic resin having sound absorption characteristics |
| 02/07/2007 | EP1749261A2 Multi-factor security system with portable devices and security kernels |
| 02/07/2007 | CN2867525Y Sliding-cover type portable multimedia player |
| 02/07/2007 | CN1910700A DQS for data from a memory array |
| 02/07/2007 | CN1909114A 半导体存储器件 A semiconductor memory device |
| 02/07/2007 | CN1909108A Sense amplifier with input offset compensation |
| 02/06/2007 | US7174489 Semiconductor memory test device |
| 02/06/2007 | US7174445 Flash memory card with enhanced operating mode detection and user-friendly interfacing system |
| 02/06/2007 | US7174415 Specialized memory device |
| 02/06/2007 | US7174409 System and method for memory hub-based expansion bus |
| 02/06/2007 | US7173876 Semiconductor integrated circuit |
| 02/06/2007 | US7173874 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface |
| 02/06/2007 | US7173873 Device and method for breaking leakage current path |
| 02/06/2007 | US7173872 Method and apparatus for controlling a high voltage generator in a wafer burn-in test |
| 02/06/2007 | US7173871 Semiconductor memory device and method of outputting data strobe signal thereof |
| 02/06/2007 | US7173870 Dual operation mode memory device |
| 02/06/2007 | US7173869 Regulating voltages in semiconductor devices |
| 02/06/2007 | US7173868 Sense amplifier of ferroelectric memory device |
| 02/06/2007 | US7173867 Memory redundancy circuit techniques |
| 02/06/2007 | US7173866 Circuit for generating data strobe signal in DDR memory device, and method therefor |
| 02/06/2007 | US7173865 Stacked die memory depth expansion |
| 02/06/2007 | US7173864 Data latch circuit and semiconductor device using the same |
| 02/06/2007 | US7173863 Flash controller cache architecture |
| 02/06/2007 | US7173856 Sense amplifier for a non-volatile memory device |
| 02/06/2007 | US7173855 Current limiting antifuse programming path |
| 02/06/2007 | US7173845 User RAM flash clear |
| 02/06/2007 | US7173463 Generating multi-phase clock signals using hierarchical delays |
| 02/06/2007 | US7173457 Silicon-on-insulator sense amplifier for memory cell |
| 02/06/2007 | US7173327 Clock distribution networks and conductive lines in semiconductor integrated circuits |
| 02/01/2007 | WO2007013984A1 High speed array pipeline architecture |
| 02/01/2007 | WO2007013860A1 System and method for modifying media content playback based on an intelligent random selection |
| 02/01/2007 | WO2006042057B1 Distributed programmed memory cells used as memory reference currents |
| 02/01/2007 | WO2006023146A3 Self-adaptive program delay circuitry for programmable memories |
| 02/01/2007 | US20070028029 Method and apparatus for data transfer |
| 02/01/2007 | US20070025174 Dual port semiconductor memory device |
| 02/01/2007 | US20070025172 Memory |