| Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008) |
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| 01/02/2008 | EP1417686B1 Random-access memory devices comprising a dioded buffer |
| 01/02/2008 | EP1328942A4 Method and system for hiding refreshes in a dynamic random access memory |
| 01/02/2008 | CN101099217A Multi-level ono flash program algorithm for threshold width control |
| 01/02/2008 | CN101099113A Silicon-containing photosensitive composition, method for forming thin film pattern using same, protective film for electronic device, gate insulating film and thin film transistor |
| 01/02/2008 | CN101097989A Memory cell with memory material insulation and manufacturing method |
| 01/02/2008 | CN101097987A Magnetic recording element and magnetic memory |
| 01/02/2008 | CN101097777A Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof |
| 01/02/2008 | CN101097776A Nonvolatile memory cell and memory system |
| 01/02/2008 | CN100359683C Semiconductor device with punctured wiring and its production method |
| 01/02/2008 | CN100359669C Method and circuit arrangement for resetting an integrated circuit |
| 01/02/2008 | CN100359604C Semiconductor storage device |
| 01/02/2008 | CN100359603C Method of programming, reading and erasing of non volatile storage with multi stage output current |
| 01/02/2008 | CN100359601C Semiconductor integrated circuit and nonvolatile memory element |
| 01/02/2008 | CN100359600C Device and method for using complementary bits in memory array |
| 01/02/2008 | CN100359599C Power-supply device and its power supply method |
| 01/02/2008 | CN100359598C Interleaving controller using non-volatile iron electric memory |
| 01/02/2008 | CN100359597C Memory cell component and production method thereof |
| 01/02/2008 | CN100359596C Semiconductor memory having enhanced testing power |
| 01/02/2008 | CN100359566C Method for reactive sputter deposition of a magnesium oxide (mgo) tunnel barrier in a magnetic tunnel junction |
| 01/02/2008 | CN100359492C System, apparatus, and method for a flexible DRAM architecture |
| 01/02/2008 | CN100359478C Safe write to multiply-redundant storage |
| 01/01/2008 | US7315970 Semiconductor device to improve data retention characteristics of DRAM |
| 01/01/2008 | US7315870 Memory controller, flash memory system, and method for recording data on flash memory |
| 01/01/2008 | US7315792 Temperature detector providing multiple detected temperature points using single branch and method of detecting shifted temperature |
| 01/01/2008 | US7315475 Non-volatile semiconductor memory device |
| 01/01/2008 | US7315474 Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays |
| 01/01/2008 | US7315473 Semiconductor storage device having page copying function |
| 01/01/2008 | US7315471 Semiconductor memory device for storing multivalued data |
| 01/01/2008 | US7315470 Data storage device and associated method for writing data to, and reading data from an unpatterned magnetic layer |
| 01/01/2008 | US7315469 Control of set/reset pulse in response to peripheral temperature in PRAM device |
| 01/01/2008 | US7315468 Thin film magnetic memory device for conducting data write operation by application of a magnetic field |
| 01/01/2008 | US7315467 Hybrid memory cell for spin-polarized electron current induced switching and writing/reading process using such memory cell |
| 01/01/2008 | US7315466 Semiconductor memory device and method for arranging and manufacturing the same |
| 01/01/2008 | US7315195 High voltage generation circuit |
| 01/01/2008 | US7315053 Magnetoresistive effect element and magnetic memory device |
| 12/27/2007 | WO2007149678A2 Programming defferently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory |
| 12/27/2007 | WO2007149677A2 Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| 12/27/2007 | WO2007149003A1 Method for nondestructively reading information in ferroelectric memory elements |
| 12/27/2007 | WO2004097835A3 Nonvolatile memory structure with high speed high bandwidth and low voltage |
| 12/27/2007 | US20070297270 Semiconductor integrated circuit device |
| 12/27/2007 | US20070297269 Memory and control unit |
| 12/27/2007 | US20070297266 Synchronous global controller for enhanced pipelining |
| 12/27/2007 | US20070297263 Semiconductor memory device capable of controlling potential level of power supply line and/or ground line |
| 12/27/2007 | US20070297261 Apparatus and method of generating power up signal of semiconductor integrated circuit |
| 12/27/2007 | US20070297260 Controlling execution of additional function during a refresh operation in a semiconductor memory device |
| 12/27/2007 | US20070297259 Memory |
| 12/27/2007 | US20070297257 Semiconductor memory device capable of canceling out noise development |
| 12/27/2007 | US20070297254 Method to Identify or Screen VMIN Drift on Memory Cells During Burn-In or Operation |
| 12/27/2007 | US20070297251 Semiconductor memory device having memory block configuration |
| 12/27/2007 | US20070297247 Method for programming non-volatile memory using variable amplitude programming pulses |
| 12/27/2007 | US20070297245 System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| 12/27/2007 | US20070297242 Negative potential discharge circuit and method thereof |
| 12/27/2007 | US20070297241 Method and Structure for Operating Memory Devices on Fringes of Control Gate |
| 12/27/2007 | US20070297240 Methods and Structures for Expanding a Memory Operation Window and Reducing a Second Bit Effect |
| 12/27/2007 | US20070297239 Memory device with a nonvolatile memory array |
| 12/27/2007 | US20070297238 Voltage regulator for flash memory device |
| 12/27/2007 | US20070297237 Memory control circuit, microcomputer, and data rewriting method |
| 12/27/2007 | US20070297236 Semiconductor memory device |
| 12/27/2007 | US20070297235 Method of forming a programmable voltage regulator and structure therefor |
| 12/27/2007 | US20070297234 Non-Volatile Memory And Method With Bit Line To Bit Line Coupled Compensation |
| 12/27/2007 | US20070297233 Nand flash memory and data programming method thereof |
| 12/27/2007 | US20070297232 Nonvolatile semiconductor memory |
| 12/27/2007 | US20070297230 Non-volatile memory structure |
| 12/27/2007 | US20070297229 Flash memory device including multi-buffer block |
| 12/27/2007 | US20070297228 Nonvolatile memory device |
| 12/27/2007 | US20070297227 Multi-Level Cell Memory Structures with Enlarged Second Bit Operation Window |
| 12/27/2007 | US20070297226 Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| 12/27/2007 | US20070297224 MOS based nonvolatile memory cell and method of operating the same |
| 12/27/2007 | US20070297223 Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells having enhanced read and write margins |
| 12/27/2007 | US20070297222 MRAM cell using multiple axes magnetization and method of operation |
| 12/27/2007 | US20070297221 Memory cell programmed using a temperature controlled set pulse |
| 12/27/2007 | US20070297220 Magnetoresistive element and magnetic memory |
| 12/27/2007 | US20070297219 Magnetoresistive memory cell, methods of programming a magnetoresistive memory cell and methods of reading a magnetoresistive memory cell |
| 12/27/2007 | US20070297218 Magnetic tunnel junction with enhanced magnetic switching characteristics |
| 12/27/2007 | US20070297217 Method and circuit arrangement for operating a volatile random access memory as a detector |
| 12/27/2007 | US20070297216 Self-assembly of molecular devices |
| 12/27/2007 | US20070297215 Semiconductor memory device and method of operating the semiconductor memory device |
| 12/27/2007 | US20070297214 Semiconductor device |
| 12/27/2007 | US20070297213 Forming a carbon layer between phase change layers of a phase change memory |
| 12/27/2007 | US20070297212 Reducing the effect of write disturbs in polymer memories |
| 12/27/2007 | US20070297101 Magnetoresistive element and magnetic memory device |
| 12/27/2007 | US20070296406 Current Induced Magnetoresistance Device |
| 12/27/2007 | US20070296033 Non-volatile memory device having four storage node films and methods of operating and manufacturing the same |
| 12/27/2007 | US20070296019 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same |
| 12/27/2007 | US20070296007 Shared ground contact isolation structure for high-density magneto-resistive RAM |
| 12/27/2007 | DE10318771B4 Integrierte Speicherschaltung mit einer Redundanzschaltung sowie ein Verfahren zum Ersetzen eines Speicherbereichs An integrated circuit memory having a redundancy circuit and a method for replacing a memory area |
| 12/27/2007 | DE102007028246A1 Magneto-resistive RAM cell, has metal-bit line supplying external magnetic field to magneto-resistive RAM-cell stack, where effective anisotropy-field and magnetic field form non-zero-angle relative to each other |
| 12/27/2007 | DE102007023533A1 Non volatile multi-bit memory unit for use in multi-bit flash memory system of e.g. mobile terminal, has cache memory with random access memory and electrically coupled with page buffer that comprises set of buffers |
| 12/27/2007 | DE102006033707A1 Voltage generator circuit for use in electronic memory device e.g. non-volatile phase change memory, has capacitor circuit with three capacitor-current passage units that are controlled such that passage units are opened sequentially |
| 12/27/2007 | DE102006029169A1 Memory module, has pulse generator, which contains impulse timer for presetting fixed time for length of split screening impulse and another impulse timer for presetting frequency dependent proportional time for clock signal cycle |
| 12/27/2007 | DE102006028483A1 Memory accessing method involves accessing memory cell arranged in cell field elements of memory and address of relevant cell field elements lies at activation device of memory |
| 12/26/2007 | EP1870903A2 Memory cell programmed using a temperature controlled set pulse |
| 12/26/2007 | EP1870902A2 Semiconductor memory device and storage method thereof |
| 12/26/2007 | EP1870901A1 Page buffer for multi-level nand flash memories |
| 12/26/2007 | EP1869543A1 Method and system for storing logical data blocks into flash-blocks in multiple non-volatile memories which are connected to at least one common data i/o bus |
| 12/26/2007 | CN101093850A Memory device and method for fabricating the memory device |
| 12/26/2007 | CN101093836A Manufacturing method of memory, and memory |
| 12/26/2007 | CN101093834A Layout structure of non-volatile memory |
| 12/26/2007 | CN101093727A Method of flash memory for updating data |
| 12/26/2007 | CN101093725A Method for operating non-volatile memory element |