Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
10/2007
10/30/2007US7289358 MTP NVM elements by-passed for programming
10/30/2007US7289357 Isolation structure for deflectable nanotube elements
10/30/2007US7289355 Pre-written volatile memory cell
10/30/2007US7289354 Memory array with a delayed wordline boost
10/30/2007US7289353 Systems and methods for adjusting programming thresholds of polymer memory cells
10/30/2007US7289352 Semiconductor storage device
10/30/2007US7289351 Method of programming a resistive memory device
10/30/2007US7289350 Electronic device with a memory cell
10/30/2007US7289346 Semiconductor integrated circuit
10/30/2007US7289344 Reverse coupling effect with timing information for non-volatile memory
10/30/2007US7289335 Force distributing spring element
10/30/2007US7289156 Optical data card reader
10/30/2007US7289142 Monolithic integrated circuit having a number of programmable processing elements
10/30/2007US7288957 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
10/30/2007US7288781 Programmable structure, an array including the structure, and methods of forming the same
10/30/2007US7287836 Ink jet printhead with circular cross section chamber
10/30/2007US7287834 Micro-electromechanical ink ejection device with an elongate actuator
10/30/2007US7287827 Printhead incorporating a two dimensional array of ink ejection ports
10/30/2007US7287702 Card reader
10/25/2007WO2007121025A1 Cycle count storage methods and systems
10/25/2007WO2007120721A2 Non-volatile memory in cmos logic process and method of operation thereof
10/25/2007WO2007119748A1 Magnetic random access memory and method for manufacturing the same
10/25/2007WO2007103045A3 Nand memory device column charging
10/25/2007WO2007008699A3 Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements
10/25/2007US20070247956 Semiconductor memory device
10/25/2007US20070247954 Memory device with shared reference and method
10/25/2007US20070247952 Semiconductor memory device and semiconductor integrated circuit device
10/25/2007US20070247949 Semiconductor memory device and refresh method for the same
10/25/2007US20070247944 Integrated Semiconductor Memory with Refreshing of Memory Cells
10/25/2007US20070247941 Semiconductor memory device
10/25/2007US20070247940 High speed sensing amplifier for an mram cell
10/25/2007US20070247939 Mram array with reference cell row and methof of operation
10/25/2007US20070247934 High-Performance Flash Memory Data Transfer
10/25/2007US20070247924 Methods for erasing memory devices and multi-level programming memory device
10/25/2007US20070247923 Methods for erasing and programming memory devices
10/25/2007US20070247922 A reliable method for erasing a flash memory
10/25/2007US20070247918 Semiconductor Integrated Circuit
10/25/2007US20070247917 Method for programming a memory device suitable to minimize floating gate coupling and memory device
10/25/2007US20070247916 Systems for Variable Reading in Non-Volatile Memory
10/25/2007US20070247915 Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide
10/25/2007US20070247914 Non-Volatile Memory In CMOS Logic Process And Method Of Operation Thereof
10/25/2007US20070247913 Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device
10/25/2007US20070247912 Semiconductor memory device improved in data writing
10/25/2007US20070247911 Method of measuring a channel boosting voltage in a nand flash memory device
10/25/2007US20070247910 NAND erase block size trimming apparatus and method
10/25/2007US20070247909 Method and system for flash memory devices
10/25/2007US20070247907 Reduction of leakage current and program disturbs in flash memory devices
10/25/2007US20070247905 Method and apparatus to protect nonvolatile memory from viruses
10/25/2007US20070247903 Reading circuit and method for a nonvolatile memory device
10/25/2007US20070247901 Mesoscopic Magnetic Body Having Circular Single Magnetic Domain Structure, its Production Method, and Magnetic Recording Device Using the Same
10/25/2007US20070247900 3-parameter switching technique for use in MRAM memory arrays
10/25/2007US20070247899 Programming a normally single phase chalcogenide material for use as a memory or FPLA
10/25/2007US20070247898 Memory having storage locations within a common volume of phase change material
10/25/2007US20070247897 Partitioned random access and read only memory
10/25/2007US20070247896 Static random access memory cell with improved stability
10/25/2007US20070247895 Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
10/25/2007US20070247894 Method of driving storage device
10/25/2007US20070247893 Non-volatile memory architecture employing bipolar programmable resistance storage elements
10/25/2007US20070247892 Circuit and a method of determining the resistive state of a resistive memory cell
10/25/2007US20070247891 Over-driven access method and device for ferroelectric memory
10/25/2007US20070247887 Semiconductor device having non-volatile memory and method of fabricating the same
10/25/2007US20070247495 Continuous injet printers
10/25/2007US20070246767 Semiconductor device formed on a SOI substrate
10/25/2007DE19958614B4 Decodierschaltung und Decodierverfahren derselben Decoding circuit and decoding method thereof
10/25/2007DE19914986B4 Vorrichtung zum Verzögern eines Taktsignals Means for delaying a clock signal
10/25/2007DE10333280B4 Halbleiter-Speicherbauelement, Vorrichtung mit Halbleiter-Speicherbauelement und Verfahren zum Betrieb eines Halbleiter-Speicherbauelements, wobei Speicherzellen aktiviert, und fallweise vorzeitig deaktiviert werden Be semiconductor memory device, device with semiconductor memory device and method of operating a semiconductor memory device, wherein memory cells are activated and deactivated from case to case prematurely
10/25/2007DE10234388B4 Halbleiterbauelement mit Doppelspannungserzeugung und Betriebsverfahren hierfür A semiconductor device with a double voltage generating and operating method therefor
10/25/2007DE102007013759A1 Memory e.g. dynamic RAM, for use in electrical system, has output pointer control making output pointer to be available based on external clock signal and updating pointer based on written signals such that pointer points to valid data
10/25/2007DE102007010547A1 System und Verfahren zum Steuern einer konstanten Leistungs-Ableitung System and method for controlling a constant power dissipation
10/25/2007DE10051167B4 Anordnung zur Fuseinitialisierung Arrangement for Fuseinitialisierung
10/25/2007DE10051164B4 Verfahren zur Maskierung von DQ-Bits A method for masking DQ bits
10/24/2007EP1550039A4 Dynamic memory supporting simultaneous refresh and data-access transactions
10/24/2007EP1433181B1 Current source and drain arrangement for magnetoresistive memories (mrams)
10/24/2007EP1282464A4 High-density non-volatile memory devices incorporating thiol-derivatized porphyrin trimers
10/24/2007EP1192666B1 Memory cell arrangement
10/24/2007CN101061550A Read method and sensing device
10/24/2007CN101061549A System and method for expanding a pulse width
10/24/2007CN101060161A Phase change memory cell with vacuum spacer
10/24/2007CN101060160A Memory element and memory
10/24/2007CN101060012A Circuit and a method of determining the resistive state of a resistive memory cell
10/24/2007CN101060011A Data writing method
10/24/2007CN100345300C Common bit/common source line high density 1T1RR-RAM array and operation method
10/24/2007CN100345294C Fuse circuit
10/24/2007CN100345283C Method and system for self-convergent erase in charge trapping memory cells
10/24/2007CN100345218C Output device for DRAM
10/24/2007CN100345217C Sensing circuit of single bit line semiconductor memory element
10/24/2007CN100345216C dynamic random access memory (RAM) for high-speed data access
10/24/2007CN100345215C Sensing device for a passive matrix memory and a read method for use therewith
10/24/2007CN100345214C Magnetic yoke structure capable of reducing programming energy consumption for MRAM apparatus and producing method thereof
10/24/2007CN100345213C System and method for early write to memory by holding bitline at fixed potential
10/24/2007CN100345123C Device and method for delaying nonvolatile memory using life
10/24/2007CN100344983C Semiconductor testing circuit, semiconductor storage and semiconductor testing method
10/23/2007US7287143 Synchronous memory device having advanced data align circuit
10/23/2007US7287142 Memory device and method for arbitrating internal and external access
10/23/2007US7287119 Integrated circuit memory device with delayed write command processing
10/23/2007US7287115 Multi-chip package type memory system
10/23/2007US7286434 Semiconductor memory device with shift register-based refresh address generation circuit
10/23/2007US7286431 Memory device capable of performing high speed reading while realizing redundancy replacement
10/23/2007US7286430 Semiconductor device
10/23/2007US7286429 High speed sensing amplifier for an MRAM cell
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