Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
12/2007
12/04/2007US7304891 Apparatus and method for improving write/read endurance of non-volatile memory
12/04/2007US7304890 Double byte select high voltage line for EEPROM memory block
12/04/2007US7304889 Serially sensing the output of multilevel cell arrays
12/04/2007US7304888 Reverse-bias method for writing memory cells in a memory array
12/04/2007US7304887 Method and apparatus for multi-plane MRAM
12/04/2007US7304886 Writing driver circuit of phase-change memory
12/04/2007US7304885 Phase change memories and/or methods of programming phase change memories using sequential reset control
12/04/2007US7304884 Semiconductor memory device
12/04/2007US7304883 Semiconductor integrated circuit
12/04/2007US7304882 Circuits for driving FRAM
12/04/2007US7304881 Ferroelectric memory with wide operating voltage and multi-bit storage per cell
12/04/2007US7304880 Electric switch and memory device using the same
12/04/2007US7304515 Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process
12/04/2007US7304364 Embossed mask lithography
12/04/2007US7304357 Devices having horizontally-disposed nanofabric articles and methods of making the same
12/04/2007US7304345 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
12/04/2007US7303262 Ink jet printhead chip with predetermined micro-electromechanical systems height
12/04/2007US7303254 Print assembly for a wide format pagewidth printer
11/2007
11/29/2007WO2007137062A2 Methods and apparatus to provide voltage control for sram write assist circuits
11/29/2007WO2007137055A2 High density magnetic memory cell layout for spin transfer torque magnetic memories utilizing donut shaped transistors
11/29/2007WO2007136944A2 Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices
11/29/2007WO2007136350A1 Organic memory device and method of its manufacture
11/29/2007WO2007135660A1 Method of storing data in a multi-bit-cell flash memory
11/29/2007WO2007098044A8 Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same
11/29/2007WO2007089558A3 Method to increase charge retention of non-volatile memory
11/29/2007US20070274150 Non-volatile memory control
11/29/2007US20070274146 TRAS adjusting circuit for self-refresh mode in a semiconductor device
11/29/2007US20070274145 Refresh control circuit in semiconductor memory apparatus and method of controlling period of refresh signal using the same
11/29/2007US20070274136 Semiconductor integrated circuit device
11/29/2007US20070274133 Flash memory device and related high voltage generating circuit
11/29/2007US20070274132 Discharge order control circuit and memory device
11/29/2007US20070274129 Data processing device
11/29/2007US20070274127 Semiconductor nonvolatile storage circuit
11/29/2007US20070274125 Enhanced Programming Performance in a Nonvolatile Memory Device Having a Bipolar Programmable Storage Element
11/29/2007US20070274124 Semiconductor memory device with improved resistance to disturbance and improved writing characteristic
11/29/2007US20070274122 Memory device having open bit line structure and method of sensing data therefrom
11/29/2007US20070274121 Multi-level memory cell having phase change element and asymmetrical thermal boundary
11/29/2007US20070274120 CBRAM cell with a reversible conductive bridging mechanism
11/29/2007US20070274119 Over-driven access method and device for ferroelectric memory
11/29/2007US20070272960 Ferroelectric memory transistor with conductive oxide gate structure
11/29/2007DE19545743B4 Halbleiterspeichervorrichtung mit Speicherzellenmatrix A semiconductor memory device having memory cell array
11/29/2007DE10227222B4 Halbleiterspeicherbauelement und Wortleitungsauswahlverfahren hierfür A semiconductor memory device, and word line selection method therefor
11/29/2007DE10212962B4 Halbleiterspeicherzelle mit Zugriffstransistor auf der Grundlage eines organischen Halbleitermaterials und Halbleiterspeichereinrichtung A semiconductor memory cell having access transistors on the basis of an organic semiconductor material and the semiconductor memory device
11/28/2007EP1859451A2 Method of achieving wear leveling in flash memory using relative grades
11/28/2007EP1859448A1 Non-volatile memory and method with power-saving read and program-verify operations
11/28/2007CN101079616A Oscillator circuit generating oscillating signal having stable cycle
11/28/2007CN101079469A MgO dual-potential magnetic tunnel structure with quanta effect and its purpose
11/28/2007CN101079438A Single-mask phase change memory element
11/28/2007CN101079319A Memory device driving circuit
11/28/2007CN101079318A SRAM unit and array
11/28/2007CN101079317A Low power balance code using data bus inversion
11/28/2007CN101079316A Semiconductor memory device with temperature sensing device capable of minimizing power consumption in refresh
11/28/2007CN101079315A Memory
11/28/2007CN101079314A Structure and access method of magnetic storage unit and magnetic memory circuit
11/28/2007CN100352168C Data transfer control device and electronic instrument
11/28/2007CN100352039C Ferroelectric memory device and its mfg. method
11/28/2007CN100351949C Data retention circuit
11/28/2007CN100351948C Semiconductor memory
11/28/2007CN100351947C Biphase precharging circuit and its composite eliminating leakage current circuit
11/28/2007CN100351946C Magnet logic element and magnet logic element array
11/28/2007CN100351945C Magnetoresistive element and magnetic memory thereof
11/28/2007CN100351944C Dynamic memory cell refreshing method for memory circuit, and memory circuit
11/28/2007CN100351943C Mixed resistive cross point memory unit array and its making process
11/27/2007US7301849 System for reducing row periphery power consumption in memory devices
11/27/2007US7301848 Apparatus and method for supplying power in semiconductor device
11/27/2007US7301833 Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device
11/27/2007US7301830 Semiconductor memory device and semiconductor device and semiconductor memory device control method
11/27/2007US7301829 Semiconductor storage apparatus
11/27/2007US7301820 Non-volatile memory dynamic operations
11/27/2007US7301819 ROM with a partitioned source line architecture
11/27/2007US7301818 Hole annealing methods of non-volatile memory cells
11/27/2007US7301816 Read operation for non-volatile storage that includes compensation for coupling
11/27/2007US7301815 Semiconductor memory device comprising controllable threshould voltage dummy memory cells
11/27/2007US7301814 System and method for avoiding offset in and reducing the footprint of a non-volatile memory
11/27/2007US7301813 Compensating for coupling during read operations of non-volatile memory
11/27/2007US7301812 Boosting to control programming of non-volatile memory
11/27/2007US7301811 Cost efficient nonvolatile SRAM cell
11/27/2007US7301810 Compensating for coupling during read operations of non-volatile memory
11/27/2007US7301809 Nonvolatile semiconductor memory
11/27/2007US7301808 Read operation for non-volatile storage that includes compensation for coupling
11/27/2007US7301807 Writable tracking cells
11/27/2007US7301806 Non-volatile semiconductor memory device adapted to store a multi-valued in a single memory cell
11/27/2007US7301805 Pipelined programming of non-volatile memories using early data
11/27/2007US7301804 NROM memory cell, memory array, related devices and methods
11/27/2007US7301803 Bipolar reading technique for a memory cell having an electrically floating body transistor
11/27/2007US7301802 Circuit arrays having cells with combinations of transistors and nanotube switching elements
11/27/2007US7301801 Tuned pinned layers for magnetic tunnel junctions with multicomponent free layers
11/27/2007US7301800 Multi-bit magnetic random access memory element
11/27/2007US7301799 Memory cell array
11/27/2007US7301798 Random access memory cell of reduced size and complexity
11/27/2007US7301797 Method of operating semiconductor integrated circuit including SRAM block and semiconductor integrated circuit including SRAM block
11/27/2007US7301796 Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets
11/27/2007US7301795 Accelerated low power fatigue testing of FRAM
11/27/2007US7301794 Non-volatile memory array with simultaneous write and erase feature
11/27/2007US7301793 Semiconductor memory device
11/27/2007US7301714 Method and apparatus for magnetic transfer, and magnetic recording medium
11/27/2007US7301199 Nanoscale wires and related devices
11/22/2007WO2007134319A2 Multi-chip package for a flash memory
11/22/2007WO2007134301A2 Iterative memory cell charging based on reference cell value
11/22/2007WO2007134281A2 Two levels of voltage regulation supplied for logic and data programming voltage of a memory device
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