Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
11/2007
11/07/2007EP1665278A4 Nanotube-based switching elements with multiple controls and circuits made from same
11/07/2007EP1532635A4 Method of programming a multi-level memory device
11/07/2007CN101068039A Structures and methods of a bistable resistive random access memory
11/07/2007CN101068037A Methods and apparatus for thermally assisted programming of a magnetic memory device
11/07/2007CN101068036A Magnetic memory device
11/07/2007CN101068024A Thermal isolation of phase change memory cells
11/07/2007CN101068023A Phase change memory fabricated using self-aligned processing
11/07/2007CN101067967A Magnetic memory device
11/07/2007CN101067966A Semiconductor memory with resistance change element
11/07/2007CN100347787C Semiconductor memory with test mode and storing system using the same
11/07/2007CN100347786C Semiconductor memory device having memory cells requiring no refresh operations
11/07/2007CN100347785C Ferromagnetic resonance switchover for magnetic random access storage
11/07/2007CN100347748C Magnetoresistive element, magnetic head, magnetic reproducing apparatus, and magnetic memory
11/06/2007US7292953 Semiconductor memory device with ability to adjust impedance of data output driver
11/06/2007US7292499 Semiconductor device including duty cycle correction circuit
11/06/2007US7292497 Multi-bank memory
11/06/2007US7292496 Semiconductor memory circuit
11/06/2007US7292494 Internal power management scheme for a memory chip in deep power down mode
11/06/2007US7292492 SRAM, semiconductor memory device, method for maintaining data in SRAM, and electronic device
11/06/2007US7292491 Method and apparatus for controlling refresh operations in a dynamic memory device
11/06/2007US7292489 Circuits and methods of temperature compensation for refresh oscillator
11/06/2007US7292486 Methods and circuits for latency control in accessing memory devices
11/06/2007US7292481 Semiconductor storage device
11/06/2007US7292477 Nonvolatile semiconductor memory device which stores multivalue data
11/06/2007US7292475 Nonvolatile memory device and data write method for nonvolatile memory device
11/06/2007US7292474 Semiconductor integrated circuit device
11/06/2007US7292473 Method and apparatus for programming/erasing a non-volatile memory
11/06/2007US7292472 Memory device capable of stable data writing
11/06/2007US7292471 Semiconductor memory device having a voltage-controlled-oscillator-based readout circuit
11/06/2007US7292470 Thin film magnetic memory device writing data with bidirectional current
11/06/2007US7292469 Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated
11/06/2007US7292468 Magnetic random access memory
11/06/2007US7292467 Magnetic random access memory device
11/06/2007US7292466 Integrated circuit having a resistive memory
11/06/2007US7292465 Ferroelectric random access memory device, display drive integrated circuit, and electronic apparatus
11/06/2007US7292464 Ferroelectric memory device
11/06/2007US7291892 Magnetic random access memory designs with controlled magnetic switching mechanism
11/06/2007US7291878 Ultra low-cost solid-state memory
11/06/2007US7291859 Organic electronic circuit and method for making the same
11/06/2007US7291506 Magnetic memory device and method of manufacturing the same
11/06/2007US7291505 Method of manufacturing a ferroelectric device
11/06/2007US7290856 Inkjet print assembly for high volume pagewidth printing
11/01/2007WO2007124205A2 Mram array with reference cell row and method of operation
11/01/2007WO2007122565A2 Static random access memory cell
11/01/2007WO2007122564A2 Memory circuit and method for sensing a memory element
11/01/2007WO2007122083A1 Dynamic memory cell structures
11/01/2007WO2006132750A3 3-d inductor and transformer devices in mram embedded integrated circuits
11/01/2007WO2006096265A3 Fast read port for register file
11/01/2007US20070255983 Semiconductor integrated circuit and electronic device
11/01/2007US20070255919 Memory controller device having timing offset capability
11/01/2007US20070255893 Nonvolatile semiconductor memory device
11/01/2007US20070254137 Thermally Conducting Multi-Layer Film
11/01/2007US20070253269 Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh
11/01/2007US20070253258 Methods to resolve hard-to-erase condition in charge trapping non-volatile memory
11/01/2007US20070253256 Memory voltage cycle adjustment
11/01/2007US20070253255 Memory device, method for sensing a current output from a selected memory cell and sensing circuit
11/01/2007US20070253253 Multiple select gates with non-volatile memory cells
11/01/2007US20070253250 Semiconductor memory device which stores plural data in a cell
11/01/2007US20070253248 Method for programming a reference cell
11/01/2007US20070253246 Thin film magnetic memory device provided with program element
11/01/2007US20070253245 High Capacity Low Cost Multi-Stacked Cross-Line Magnetic Memory
11/01/2007US20070253244 Magnetic random access memory
11/01/2007US20070253243 Memory array having memory cells formed from metallic material
11/01/2007US20070253242 Page mode access for non-volatile memory arrays
11/01/2007US20070253241 Method for accessing data on magnetic memory
11/01/2007US20070253240 Fault tolerant asynchronous circuits
11/01/2007US20070253239 Read-preferred SRAM cell design
11/01/2007US20070253238 Semiconductor memory device with information loss self-detect capability
11/01/2007US20070253235 Low-Voltage Ic-Circuit
11/01/2007US20070252137 Non-Volatile Ferroelectric Thin Film Device Using an Organic Ambipolar Semiconductor and Method for Processing Such a Device
10/2007
10/31/2007EP1849162A1 A single chip having a magnetoresistive memory
10/31/2007EP1849161A2 Register read for volatile memory
10/31/2007EP1151388B1 Dram refresh monitoring and cycle accurate distributed bus arbitration in a multi-processing environment
10/31/2007DE102007012177A1 Speicher mit einem Temperatursensor, dynamischer Speicher und Speicher mit einer Takteinheit sowie Verfahren zum Abtasten einer Temperatur eines Speichers Memory with a temperature sensor, a dynamic memory and having a clock unit and method for sensing a temperature of a memory
10/31/2007DE102006020098A1 Dynamic RAM memory circuit, has recreation circuit recreating memory cells based on selection information, and word line decoder selecting one of word lines depending based on address information
10/31/2007CN101065807A A novel nvram memory cell architecture that integrates conventional sram and flash cells
10/31/2007CN101064361A 存储元件以及半导体装置 Memory element and semiconductor device
10/31/2007CN101064359A Non-volatile memory devices including variable resistance material
10/31/2007CN101064358A Magneto-resistive element and method of manufacturing the same
10/31/2007CN101064331A Phase change memory fabricated using self-aligned processing
10/31/2007CN101064189A Static random access memory cell with improved stability and its formation method
10/31/2007CN101064188A Semiconductor framework and sram storage element
10/31/2007CN101064187A Semiconductor integrated circuit
10/31/2007CN101064186A Memory
10/31/2007CN101064185A Memory
10/31/2007CN101064184A Magnetic random access memory element, and method for writing and producing
10/31/2007CN101064182A Circuits for sensing resistance states of a memory cell and its method
10/31/2007CN101064114A Magnetoresistive effect element and magnetic memory
10/31/2007CN100346422C Semiconductor memory device and control method thereof
10/31/2007CN100346421C Magnetic random access storage device
10/31/2007CN100346317C Information processing device using variable operation frequency
10/30/2007US7290078 Serial memory comprising means for protecting an extended memory array during a write operation
10/30/2007US7289384 Method for writing to multiple banks of a memory device
10/30/2007US7289368 Control of voltages during erase and re-program operations of memory cells
10/30/2007US7289367 Semiconductor memory device capable of carrying out stable operation
10/30/2007US7289366 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
10/30/2007US7289362 Erasable and programmable non-volatile cell
10/30/2007US7289361 Semiconductor integrated circuit and nonvolatile memory element
10/30/2007US7289360 Multi-state memory
10/30/2007US7289359 Systems and methods for using a single reference cell in a dual bit flash memory
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