Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
09/2014
09/18/2014US20140269123 Semiconductor memory device and refresh method thereof
09/18/2014US20140269119 Synchronous semiconductor memory device having delay locked loop circuit and method of controlling the delay locked loop circuit
09/18/2014US20140269042 Self-referenced Magnetic Random Access Memory
09/18/2014US20140269041 Emulation of static random access memory (sram) by magnetic random access memory (mram)
09/18/2014US20140269040 Pulse programming techniques for voltage-controlled magnetoresistive tunnel junction (mtj)
09/18/2014US20140269039 Electronic device and variable resistance element
09/18/2014US20140269038 Magnetic memory
09/18/2014US20140269037 Magnetic memory element and nonvolatile memory device
09/18/2014US20140269036 Magnetic memory devices and methods of writing data to the same
09/18/2014US20140269035 Cross point array mram having spin hall mtj devices
09/18/2014US20140269034 Integrated capacitor based power distribution
09/18/2014US20140269033 Magnetic memory
09/18/2014US20140269032 Architecture for magnetic memories including magnetic tunneling junctions using spin-orbit interaction based switching
09/18/2014US20140269031 System and method of sensing a memory cell
09/18/2014US20140269030 Method and apparatus for mram sense reference trimming
09/18/2014US20140269029 Selective self-reference read
09/18/2014US20140269028 Thermally-Assisted Mram with Ferromagnetic Layers with Temperature Dependent Magnetization
09/18/2014US20140269027 Amplifier
09/18/2014US20140269025 Memory with redundant sense amplifier
09/18/2014US20140269024 Memory device and method for writing therefor
09/18/2014US20140269023 Biasing bulk of a transistor
09/18/2014US20140269022 Three-dimensional (3d) memory cell separation among 3d integrated circuit (ic) tiers, and related 3d integrated circuits (3dics), 3dic processor cores, and methods
09/18/2014US20140269021 Timing logic for memory array
09/18/2014US20140269020 System and method to regulate operating voltage of a memory array
09/18/2014US20140269019 Dual-port static random access memory (sram)
09/18/2014US20140269018 Write-Assisted Memory with Enhanced Speed
09/18/2014US20140269017 Process corner sensor for bit-cells
09/18/2014US20140269016 Multiport memory with matching address control
09/18/2014US20140269015 Use of hydrocarbon nanorings for data storage
09/18/2014US20140269014 Memory device
09/18/2014US20140269013 Memory device and semiconductor device
09/18/2014US20140269012 Ground-referenced single-ended system-on-package
09/18/2014US20140269011 Multi-phase ground-referenced single-ended signaling
09/18/2014US20140269010 Ground-referenced single-ended memory interconnect
09/18/2014US20140269009 Dram with pulsed sense amp
09/18/2014US20140268987 Thermally-Assisted Mram with Ferromagnetic Layers with Temperature Dependent Magnetization
09/18/2014US20140268483 Ferroelectric Capacitor With Improved Fatigue and Breakdown Properties
09/18/2014DE112011105998T5 Speicheroperationen unter Verwendung von Systemtemperatursensordaten Memory operations using system temperature sensor data
09/18/2014DE102014103276A1 Architektur für magnetische Speicher mit magnetischen Tunnelkontakten, die auf Spin-Bahn-Wechselwirkung basierendes Schalten verwendet Architecture for magnetic storage with magnetic tunnel junctions, the Turn-based spin-orbit interaction used
09/18/2014DE102014103119A1 Magnetische übergänge mit einfügungsschichten und magnetische speicher mit den magnetischen übergängen Magnetic transitions with inset layers and magnetic memory with the magnetic transitions
09/17/2014EP2779173A2 2T and flash memory array
09/17/2014EP2777045A1 Circuit for reverse biasing inverters for reducing the power consumption of an sram memory
09/16/2014US8839080 Methods of performing error detection/correction in nonvolatile memory devices
09/16/2014US8839075 Interference-aware assignment of programming levels in analog memory cells
09/16/2014US8839058 Multi-site testing of computer memory devices and serial IO ports
09/16/2014US8838883 System and method of adjusting a programming step size for a block of a memory
09/16/2014US8837252 Memory decoder circuit
09/16/2014US8837251 Semiconductor device with low voltage programming/erasing operation
09/16/2014US8837246 Memory device, operation method thereof and memory system having the same
09/16/2014US8837245 Memory cell array latchup prevention
09/16/2014US8837235 Local evaluation circuit for static random-access memory
09/16/2014US8837234 Voltage control method to minimize a coupling noise between adjacent global bit lines during read-while operation and memory device using the same
09/16/2014US8837226 Memory including a reduced leakage wordline driver
09/16/2014US8837224 Nonvolatile memory device, operating method thereof and memory system including the same
09/16/2014US8837223 Nonvolatile semiconductor memory device and method for manufacuring the same
09/16/2014US8837221 Write bias condition for 2T-string NOR flash cell
09/16/2014US8837220 Nonvolatile memory and manipulating method thereof
09/16/2014US8837217 Memory storage apparatus, and memory controller and power control method
09/16/2014US8837215 Operating method and data read method in nonvolatile memory device
09/16/2014US8837213 Semiconductor memory device which stores multilevel data
09/16/2014US8837212 Electronic devices including two or more substrates electrically connected together and methods of forming such electronic devices
09/16/2014US8837211 Robust initialization with phase change memory cells in both configuration and array
09/16/2014US8837210 Differential sensing method and system for STT MRAM
09/16/2014US8837209 Magnetic memory cell and magnetic random access memory
09/16/2014US8837208 Magnetic tunnel junction device with diffusion barrier layer
09/16/2014US8837207 Static memory and memory cell thereof
09/16/2014US8837206 Memory device
09/16/2014US8837205 Multi-port register file with multiplexed data
09/16/2014US8837204 Four-transistor and five-transistor BJT-CMOS asymmetric SRAM cells
09/16/2014US8837203 Semiconductor device
09/16/2014US8837202 Semiconductor memory device and method for driving the same
09/16/2014US8837201 Programming an array of resistance random access memory cells using unipolar pulses
09/16/2014US8837200 Nonvolatile semiconductor memory device and read method for the same
09/16/2014US8837199 Semiconductor memory device
09/16/2014US8837198 Multi-bit resistance measurement
09/16/2014US8837197 Circuit for generating write signal, variable resistance memory device, and method for programming variable resistance memory
09/16/2014US8837196 Single layer complementary memory cell
09/16/2014US8837195 Systems and methods for reading ferroelectric memories
09/16/2014US8837194 Data holding device and logic operation circuit using the same
09/16/2014US8837192 N-bit rom cell
09/16/2014US8837188 Content addressable memory row having virtual ground and charge sharing
09/16/2014US8836809 Quad-core image processor for facial detection
09/16/2014US8836410 Internal voltage compensation circuit
09/16/2014US8836060 Spin device, driving method of the same, and production method of the same
09/16/2014US8836030 Methods of forming memory cells, memory cells, and semiconductor devices
09/12/2014WO2014138248A1 Power supply brownout protection circuit and method for embedded fram
09/12/2014WO2014138091A1 Calibration of single-ended high-speed interfaces
09/12/2014WO2014138081A1 Calibration of single-ended high-speed interfaces
09/12/2014WO2014137937A1 Enhanced dynamic read process with single-level cell segmentation
09/12/2014WO2014137645A2 Write sequence providing write abort protection
09/12/2014WO2014137631A1 Internal data load for non-volatile storage
09/12/2014WO2014135758A1 Memory comprising a circuit for detecting a transient pulse on a line of the memory
09/12/2014WO2014135385A1 Self-referenced mram cell that can be read with reduced power consumption
09/11/2014US20140258606 Storage control device, storage device, information processing system, and storage control method
09/11/2014US20140254298 Variable dynamic memory refresh
09/11/2014US20140254295 Memory device and method for driving the same
09/11/2014US20140254274 Semiconductor memory device
09/11/2014US20140254259 Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor
09/11/2014US20140254255 Mram wtih metal gate write conductors
09/11/2014US20140254253 Memory element and memory device
1 ... 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ... 761