Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
10/2011
10/20/2011US20110255328 Semiconductor memory device
10/19/2011EP2378664A1 Magnetic device
10/19/2011EP2377127A1 Variable memory refresh devices and methods
10/19/2011EP2377126A1 A novel free lyer/capping layer for high performance mram mt j
10/19/2011EP1610339B1 Magnetic memory device and read method thereof
10/19/2011EP1590738B1 Distributed memory computing environment and implantation thereof
10/19/2011CN1925058B Semiconductor device
10/19/2011CN102224546A Stram with compensation element
10/19/2011CN102222688A Bidirectional controllable rectifying resistance-variable memory
10/19/2011CN101475160B Carbon nanotube structure, its manufacturing and operating method
10/19/2011CN101441888B Method and apparatus for simultaneous differential data sensing and capture in a high speed memory
10/19/2011CN101154461B Nonvolatile semiconductor memory device
10/18/2011US8042022 Method, system, and apparatus for distributed decoding during prolonged refresh
10/18/2011US8041916 Data storage device and method of operating the same
10/18/2011US8040751 Semiconductor memory device
10/18/2011US8040738 Method and apparatus for performing semiconductor memory operations
10/18/2011US8040737 Gain control for read operations in flash memory
10/18/2011US8040735 Semiconductor memory device capable of detecting write completion at high speed
10/18/2011US8040734 Current-mode sense amplifying method
10/18/2011US8040733 Non-volatile memory device and method of operating the same
10/18/2011US8040732 NAND memory device column charging
10/18/2011US8040731 Nonvolatile semiconductor memory
10/18/2011US8040730 Nonvolatile memory device
10/18/2011US8040728 Semiconductor integrated circuit
10/18/2011US8040727 Flash EEprom system with overhead data stored in user data sectors
10/18/2011US8040726 Flash memory device and layout method of the flash memory device
10/18/2011US8040724 Magnetic domain wall random access memory
10/18/2011US8040722 Charge mapping memory array formed of materials with mutable electrical characteristics
10/18/2011US8040721 Creating short program pulses in asymmetric memory arrays
10/18/2011US8040720 Phase-change memory device including biasing circuit
10/18/2011US8040719 Nonvolatile memory devices having bit line discharge control circuits therein that provide equivalent bit line discharge control
10/18/2011US8040718 Semiconductor memory device
10/18/2011US8040717 SRAM cell and SRAM device
10/18/2011US8040716 Controlling a variable resistive memory wordline switch
10/18/2011US8040715 Semiconductor storage device
10/18/2011US8040714 Multilevel nonvolatile memory device using variable resistance
10/18/2011US8040713 Bit set modes for a resistive sense memory cell array
10/18/2011US8039298 Phase changeable memory cell array region and method of forming the same
10/13/2011WO2011127195A1 Saw-shaped multi-pulse programming for program noise reduction in memory
10/13/2011WO2011127054A1 Programmable tracking circuit for tracking semiconductor memory read current
10/13/2011WO2011127025A1 Asymmetric write scheme for magnetic bit cell elements
10/13/2011WO2011127023A1 Circuits, systems, and methods for dynamic voltage level shifting
10/13/2011WO2011125432A1 Semiconductor memory device
10/13/2011WO2011124855A1 Ram memory cell comprising a transistor
10/13/2011WO2011123936A1 Semiconductor memory device having a three-dimensional structure
10/13/2011WO2011084499A3 Techniques for reducing impact of array disturbs in a semiconductor memory device
10/13/2011US20110252290 Integrated data and header protection for tape drives
10/13/2011US20110252206 Memory programming using variable data width
10/13/2011US20110249498 Three-dimensionally stacked nonvolatile semicondutor memory
10/13/2011US20110249491 Method and apparatus for programming a magnetic tunnel junction (mtj)
10/13/2011US20110249490 Asymmetric Write Scheme for Magnetic Bit Cell Elements
10/13/2011US20110249489 Nanowire Circuits in Matched Devices
10/13/2011US20110249488 Data Cells with Drivers and Methods of Making and Operating the Same
10/13/2011US20110249487 Semiconductor memory device and semiconductor device
10/13/2011US20110249486 Resistance variable memory apparatus
10/13/2011US20110249485 Resistance-change memory
10/13/2011US20110248761 Phase Adjustment Apparatus and Method for a Memory Device Signaling System
10/13/2011US20110248325 Spin transistor, programmable logic circuit, and magnetic memory
10/13/2011DE102010003811A1 Verfahren und Anordnung zur Manipulation von in einem magnetischen Medium gespeicherten Domäneninformationen Method and apparatus for manipulating data stored in a magnetic medium domain information
10/13/2011CA2792158A1 Semiconductor memory device having a three-dimensional structure
10/12/2011EP2375464A1 Magnetoresistive element and memory device using same
10/12/2011EP2374134A2 Spare block management in non-volatile memories
10/12/2011EP2374133A1 Sensing circuit and method with reduced susceptibility to spatial and temperature variations
10/12/2011EP2374132A1 Multibit multiferroic memory element
10/12/2011EP2374131A1 Spin-torque bit cell with unpinned reference layer and unidirectional write current
10/12/2011EP2374130A1 Magnetic random access memory with dual spin torque reference layers
10/12/2011EP2374129A1 Digitally-controllable delay for sense amplifier
10/12/2011EP1588373B1 Fast remanent resistive ferroelectric memory
10/12/2011CN1975928B Phase change random access memory and method of controlling read operation thereof
10/12/2011CN1975927B Phase-changeable memory device and read method thereof
10/12/2011CN1905059B Multi-port memory based on DRAM core and controlling method thereof
10/12/2011CN102216996A Semiconductor memory device
10/12/2011CN102216995A Flux-closed stram with electronically reflective insulative spacer
10/12/2011CN102216994A Stram with electronically reflective insulative spacer
10/12/2011CN102214673A Semiconductor device and method for fabricating the same
10/12/2011CN102214483A Pseudo-inverter circuit on SeOI
10/12/2011CN102214482A High-speed high-capacity solid electronic recorder
10/11/2011US8037237 Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages
10/11/2011US8037231 Memory architecture for separation of code and data in a memory device
10/11/2011US8036044 Dynamically adjustable erase and program levels for non-volatile memory
10/11/2011US8036041 Method for non-volatile memory with background data latch caching during read operations
10/11/2011US8036038 Semiconductor memory device
10/11/2011US8036031 Semiconductor device having a field effect source/drain region
10/11/2011US8036030 Multi-level cell copyback program method in a non-volatile memory device
10/11/2011US8036027 Semiconductor device and memory
10/11/2011US8036026 Semiconductor memory device and method for operating the same
10/11/2011US8036023 Single-event upset immune static random access memory cell circuit
10/11/2011US8036022 Structure and method of using asymmetric junction engineered SRAM pass gates, and design structure
10/11/2011US8036021 Semiconductor memory device
10/11/2011US8036020 Circuit for reading a charge retention element for a time measurement
10/11/2011US8036019 Resistive memory
10/11/2011US8036018 Non-volatile memory devices including stacked NAND-type resistive memory cell strings
10/11/2011US8036017 Semiconductor memory device
10/11/2011US8036015 Resistive memory
10/11/2011US8036014 Phase change memory program method without over-reset
10/11/2011US8036013 Using higher current to read a triggered phase change memory
10/11/2011US8036012 Device for controlling the activity of modules of an array of memory modules
10/06/2011WO2011123583A1 Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features
10/06/2011WO2011123279A1 Extra dummy erase pulses after shallow erase -verify to avoid sensing deep erased threshold voltage
10/06/2011WO2011120495A1 Domain-structured ferroic element, method and apparatus for generating and for controlling the electrical conductivity of domain walls at room temperature in the elements and applications of the element
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