Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
05/2002
05/23/2002WO2002041323A2 Circuit arrangement
05/23/2002WO2002041146A2 Instruction processor systems and methods
05/23/2002WO2001031789A3 Magnetic logic device having magnetic quantum dots
05/23/2002US20020062411 Input/output pad with mornitoring ability and operation method thereof
05/23/2002US20020060947 Semiconductor integrated circuit
05/23/2002US20020060944 Semiconductor integrated circuit device and method of activating the same
05/23/2002US20020060602 Bias voltage generator usable with circuit for producing low-voltage differential signals
05/23/2002US20020060592 Slew rate adjusting circuit and semiconductor device
05/23/2002US20020060590 Driving circuit for LCD
05/23/2002US20020060359 Manipulation-proof integrated circuit
05/23/2002US20020060328 Semiconductor device
05/23/2002DE10136798A1 Eingangsschnittstellenschaltung für eine integrierte Halbleiterschaltungsvorrichtung Input interface circuit for a semiconductor integrated circuit device
05/23/2002DE10056590A1 Digital signal processing and/or storing circuit for smart card controller has at least one programmable fuse formed in multiple stages
05/23/2002DE10048823C1 Treiberschaltung für PC-Bus Driver circuit for PC bus
05/23/2002DE10046806A1 Tri-State-Treiberanordnung Tri-state driver arrangement
05/23/2002CA2429028A1 Magnetic logic elements
05/22/2002CN1085440C Small aplitude signal output circuit
05/21/2002USRE37708 Programmable bandwidth voltage regulator
05/21/2002US6392855 Floating body charge monitor circuit for partially depleted SOI CMOS technology
05/21/2002US6392625 Liquid crystal display apparatus having level conversion circuit
05/21/2002US6392467 Semiconductor integrated circuit
05/21/2002US6392466 Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path
05/21/2002US6392453 Differential input buffer bias circuit
05/21/2002US6392452 Input buffer circuit for RF phase-locked loops
05/21/2002US6392451 Threshold value operation circuit, and, and gate circuit, self hold circuit, start signal generation circuit using threshold value operation circuit
05/21/2002US6392445 Decoder element for producing an output signal having three different potentials
05/21/2002US6392444 IIL reset circuit
05/21/2002US6392442 Driver circuit that compensates for skin effect losses
05/21/2002US6392441 Fast response circuit
05/21/2002US6392440 5V compliant transmission gate and the drive logic using 3.3V technology
05/21/2002US6392439 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit
05/21/2002US6392438 Programmable logic array integrated circuit devices
05/21/2002US6392437 Programmable multi-standard I/O architecture for FPGAs
05/21/2002US6392436 Programmable circuit with preview function
05/16/2002WO2002039629A2 Channel time calibration means
05/16/2002WO2002027930A3 Dynamic swing voltage adjustment
05/16/2002WO2002027929A3 Universal impedance control for wide range loaded signals
05/16/2002WO2002007400A3 Digital interface with low power consumption
05/16/2002WO2001043135A9 A prefetch write driver for a random access memory
05/16/2002US20020059555 Depopulated programmable logic array
05/16/2002US20020059501 High-availability super server
05/16/2002US20020057621 Programmable logic array device with random access memory configurable as product terms
05/16/2002US20020057620 Semiconductor integrated circuit device and method of activating the same
05/16/2002US20020057619 Semiconductor integrated circuit device and method of activating the same
05/16/2002US20020057618 Semiconductor integrated circuit device having hierarchical power source arrangement
05/16/2002US20020057612 Signal transmission circuit and semiconductor memory using the same
05/16/2002US20020057597 Current sense amplifier circuit
05/16/2002US20020057121 Trip-point adjustment and delay chain circuits
05/16/2002US20020057114 Circuit for driving gate of IGBT inverter
05/16/2002US20020057112 Nmos precharge domino logic
05/16/2002US20020057111 Random logic circuit
05/16/2002US20020057110 Path transistor circuit and method for designing the same, a device and method for optimizing logic circuits, and a computer product
05/16/2002US20020057109 Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit
05/16/2002US20020057108 Semiconductor integrated circuit
05/16/2002US20020057107 Capacitively coupled re-referencing circuit with transient correction
05/16/2002US20020057106 Data output buffer circuit usable with both PCI and PCI-X buses
05/16/2002US20020057105 Input-output buffer circuit
05/16/2002US20020057104 Method and apparatus for incorporating a multiplier into an FPGA
05/16/2002US20020057103 Interconnection and input/output resources for programable logic integrated circuit devices
05/16/2002US20020057102 Impedance controlled output circuit having multi-stage of high code selectors in semiconductor device and method for operating the same
05/16/2002US20020057100 Threshold invariant voltage detecting device
05/16/2002US20020057017 Auto-MDIX line-driver with power down loopback protection
05/16/2002DE10149691A1 Integrierte Halbleiterschaltung mit Varactorbauteilen A semiconductor integrated circuit with Varactorbauteilen
05/16/2002DE10050561A1 Integrierte Schaltung mit Schaltungsteilen mit unterschiedlicher Versorgungsspannung Integrated circuit to circuit elements with different supply voltages
05/15/2002EP1206038A1 Circuit arrangement with internal supply voltage
05/15/2002EP1205071A1 Field programmable gate array with program encryption
05/15/2002EP1205029A2 Integrated semiconductor circuit
05/15/2002EP1204990A1 An integrated circuit with metal programmable logic having enhanced reliability
05/15/2002EP1057117B1 METHOD FOR CACHEING CONFIGURATION DATA OF DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) ACCORDING TO A HIERARCHY
05/15/2002EP1057102B1 METHOD FOR CONFIGURING DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) WITHOUT PRODUCING DEADLOCKS
05/14/2002US6389557 Freezing mechanism for debugging
05/14/2002US6388916 Magnetoelectronic memory element with isolation element
05/14/2002US6388504 Integrated circuit device with switching between active mode and standby mode controlled by digital circuit
05/14/2002US6388503 Output buffer with charge-pumped noise cancellation
05/14/2002US6388499 Level-shifting signal buffers that support higher voltage power supplies using lower voltage MOS technology
05/14/2002US6388483 Semiconductor integrated circuit device and microcomputer
05/14/2002US6388475 Voltage tolerant high drive pull-up driver for an I/O buffer
05/14/2002US6388474 Semiconductor integrated circuit
05/14/2002US6388473 Logic product circuit
05/14/2002US6388470 High voltage CMOS signal driver with minimum power dissipation
05/14/2002US6388467 High voltage tolerant output driver for sustained tri-state signal lines
05/14/2002US6388466 FPGA logic element with variable-length shift register capability
05/14/2002US6388465 Reconfigurable integrated circuit with integrated debussing facilities and scalable programmable interconnect
05/14/2002US6388464 Configurable memory for programmable logic circuits
05/10/2002WO2002037783A2 Auto-mdix line-driver with power down loopback protection
05/10/2002WO2002037682A1 Circuits and sequences for enabling remote access to and control of non-adjacent cells
05/10/2002WO2002037681A1 Switching aid circuit for a logic circuit
05/10/2002WO2002037680A1 Electronic safety switching device
05/10/2002WO2002037679A2 Transmitter circuit comprising timing deskewing means
05/10/2002WO2002037678A1 Integrated circuit with output drivers
05/10/2002WO2002037572A1 Point contact array, not circuit, and electronic circuit comprising the same
05/10/2002WO2001028097A9 Heterogeneous interconnection architecture for programmable logic devices
05/09/2002US20020056058 Storage system with online manual
05/09/2002US20020056033 System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image
05/09/2002US20020056016 Apparatus and method for topography dependent signaling
05/09/2002US20020053948 Low voltage rail-to-rail CMOS input stage
05/09/2002US20020053944 Circuit configuration for switching over a receiver circuit in particular in DRAM memories and DRAM memory having the circuit configuration
05/09/2002US20020053941 Transmission gate
05/09/2002US20020053940 Temperature dependent circuit, and current generating circuit, inverter and oscillation circuit using the same
05/09/2002US20020053938 Digital electronic circuit for use in implementing digital logic functions