| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 07/02/2002 | US6414517 Input buffer circuits with input signal boost capability and methods of operation thereof |
| 07/02/2002 | US6414516 CMOS output amplifier independent of temperature, supply voltage and manufacturing quality of transistors |
| 07/02/2002 | US6414515 Failsafe interface circuit with extended drain devices |
| 07/02/2002 | US6414514 Logic device architecture and method of operation |
| 07/02/2002 | US6414363 Semiconductor device with power cutting transistors |
| 06/27/2002 | WO2002050665A1 Data processing device with a configurable functional unit |
| 06/27/2002 | WO2001086813A3 Fpga lookup table with dual ended writes for ram and shift register modes |
| 06/27/2002 | WO2001086812A3 Fpga lookup table with high speed read decoder |
| 06/27/2002 | WO2000049718A9 Global signal distribution architecture in a field programmable gate array |
| 06/27/2002 | US20020083389 Testing integrated circuits |
| 06/27/2002 | US20020083352 Level shifter control circuit with delayed switchover to low-power level shifter |
| 06/27/2002 | US20020083308 Data processing device with a configurable functional unit |
| 06/27/2002 | US20020080663 Semiconductor integrated circuit |
| 06/27/2002 | US20020079955 Circuit for generating internal power voltage in a semiconductor device |
| 06/27/2002 | US20020079951 Employing transistor body bias in controlling chip parameters |
| 06/27/2002 | US20020079949 Configurable electronic circuit |
| 06/27/2002 | US20020079942 Complementary data line driver circuits having conditional charge recycling capability and methods of operating same |
| 06/27/2002 | US20020079941 Duty cycle correction circuits that reduce distortion caused by mismatched transistor pairs |
| 06/27/2002 | US20020079929 Semiconductor integrated device, and method of designing the same |
| 06/27/2002 | US20020079927 Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuit |
| 06/27/2002 | US20020079924 Method and circuit configuration for controlling a data driver |
| 06/27/2002 | US20020079922 Dual purpose low power input circuit for a memory device interface |
| 06/27/2002 | US20020079921 Configurable logic block for PLD with logic gate for combining output with another configurable logic block |
| 06/27/2002 | US20020079545 High-voltage switching device and application to a non-volatile memory |
| 06/27/2002 | DE10062568A1 Signal detector circuit has compensated and non-compensated delay stages coupled to detection device for detecting differing delay characteristics |
| 06/27/2002 | DE10059513A1 Data driver control method has reference clock flanks preceded by fixed length interval during which data output is brought to mean level between high and low bit value levels |
| 06/26/2002 | EP1217744A1 An output buffer with constant switching current |
| 06/26/2002 | EP1217741A1 Low power circuit with slew rate adjustment |
| 06/26/2002 | EP1216506A1 Method and apparatus for reducing peak power consumption |
| 06/26/2002 | CN1355903A Interface for coupling bus node to bus line of bus system |
| 06/26/2002 | CN1355607A Circuit with protection to error-polarity connection of power supply |
| 06/26/2002 | CN1355590A Grid circuit for driving insulated gate bipolar transistor inverter |
| 06/26/2002 | CN1086815C Progrmamable logic device with regional and universal signal routing |
| 06/25/2002 | US6411554 High voltage switch circuit having transistors and semiconductor memory device provided with the same |
| 06/25/2002 | US6411550 Semiconductor integrated-circuit device |
| 06/25/2002 | US6411243 Mode control circuit |
| 06/25/2002 | US6411156 Employing transistor body bias in controlling chip parameters |
| 06/25/2002 | US6411152 Conditional clock buffer circuit |
| 06/25/2002 | US6411150 Dynamic control of input buffer thresholds |
| 06/25/2002 | US6411149 Semiconductor integrated circuit device operable with low power consumption at low power supply voltage |
| 06/25/2002 | US6411146 Power-off protection circuit for an LVDS driver |
| 06/25/2002 | US6411140 Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit |
| 06/25/2002 | US6411129 Logic circuit with output high voltage boost and method of using |
| 06/25/2002 | US6411128 Logical circuit for serializing and outputting a plurality of signal bits simultaneously read from a memory cell array or the like |
| 06/25/2002 | US6411127 Multi-level bonding option circuit |
| 06/25/2002 | US6411125 CMOS bus driver circuit |
| 06/25/2002 | US6411124 Programmable logic device logic modules with shift register capabilities |
| 06/25/2002 | US6411121 Systems and methods for adjusting signal transmission parameters of an integrated circuit |
| 06/25/2002 | US6411120 Output buffer drive circuit with initial drive for semiconductor devices |
| 06/20/2002 | WO2002049111A1 Electrical circuit comprising redundancy units, which have an increased long-time stability |
| 06/20/2002 | WO2002021693A8 Field programmable gate array and microcontroller system-on-a-chip |
| 06/20/2002 | WO2000079294A9 A method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit |
| 06/20/2002 | US20020078410 Master-slave-type scanning flip-flop circuit for high-speed operation with reduced load capacity of clock controller |
| 06/20/2002 | US20020075066 Semiconductor integrated circuit device |
| 06/20/2002 | US20020075064 Semiconductor integrated circuit |
| 06/20/2002 | US20020075060 Translating switch circuit with disabling option |
| 06/20/2002 | US20020075051 Power-off protection circuit for an lvds driver |
| 06/20/2002 | US20020075049 Output buffer circuit |
| 06/20/2002 | US20020075044 Low component circuit for reducing power dissipation capacitance |
| 06/20/2002 | US20020075038 Active leakage control technique for high performance dynamic circuits |
| 06/20/2002 | US20020075037 Digital interface with low power consumption |
| 06/20/2002 | US20020075036 Circuit for eliminating floating inputs on differential receivers |
| 06/20/2002 | US20020075035 Circuit for providing a logical output signal in accordance with crossing points of differential signals |
| 06/20/2002 | US20020075034 Arrangement for improving the ESD protection in a CMOS buffer |
| 06/20/2002 | US20020075033 Semiconductor device and control method thereof |
| 06/20/2002 | US20020075032 Skew adjusting circuit and semiconductor integrated circuit |
| 06/20/2002 | US20020074609 Data hold circuit, a semiconductor device and a method of designing the same |
| 06/20/2002 | DE10155846A1 Treiber-Schaltung für Steuerelektrode von IGBT Invertierer Driver circuit for gate of the IGBT inverter |
| 06/20/2002 | DE10059309A1 Digitale Pegelanpassung Digital level adjustment |
| 06/19/2002 | EP1215861A2 Switchable, resistive termination circuit |
| 06/19/2002 | EP1215682A2 Initializing an integrated circuit using compressed data from a remote fusebox |
| 06/19/2002 | EP1215586A2 Configuring memory and registers from a serial device |
| 06/19/2002 | EP1214789A1 Two-stage muller c-element |
| 06/19/2002 | EP1163723A4 Delay stabilization system for an integrated circuit |
| 06/19/2002 | CN1354908A Integrated circuit low leakage power circuitry for use with advanced CMOS process |
| 06/19/2002 | CN1354580A Signal transmission device suitable for fast signal transmission, circuit block and integrated circuit |
| 06/19/2002 | CN1354454A Display device with improved voltage-level converter circuit |
| 06/18/2002 | US6408195 Semiconductor integrated circuit for communication and battery saving method for the same |
| 06/18/2002 | US6407608 Clock input buffer with increased noise immunity |
| 06/18/2002 | US6407591 Self-configurable clock input buffer compatible with high-voltage single-ended and low-voltage differential clock signals |
| 06/18/2002 | US6407587 Adiabatic logic circuit |
| 06/18/2002 | US6407585 Method and apparatus for a family of self clocked dynamic circuits |
| 06/18/2002 | US6407584 Charge booster for CMOS dynamic circuits |
| 06/18/2002 | US6407583 Logic circuit having phase-controlled data receiving interface |
| 06/18/2002 | US6407582 Enhanced 2.5V LVDS driver with 1.8V technology for 1.25 GHz performance |
| 06/18/2002 | US6407581 High voltage multipurpose input/output circuit |
| 06/18/2002 | US6407578 Arrangement for reducing power dissipation in a line driver |
| 06/18/2002 | US6407576 Interconnection and input/output resources for programmable logic integrated circuit devices |
| 06/18/2002 | US6407574 Method and system for utilizing hostile-switching neighbors to improve interconnect speed for high performance processors |
| 06/18/2002 | US6407434 Hexagonal architecture |
| 06/13/2002 | WO2002047339A2 Output driver circuit with current detection |
| 06/13/2002 | WO2002046936A2 Method and apparatus for communicating with a host |
| 06/13/2002 | US20020070791 Enhanced conductivity body biased pmos driver |
| 06/13/2002 | US20020070771 Semiconductor controller device having a controlled output driver characteristic |
| 06/13/2002 | US20020070769 Reduced power consumption bi-directional buffer |
| 06/13/2002 | US20020070764 Output driver circuit with current detection |
| 06/13/2002 | US20020070758 Noise tolerant wide-fanin domino circuits |
| 06/13/2002 | US20020070757 Buffer circuit for the reception of a clock signal |
| 06/13/2002 | US20020070756 Floor plan for scalable multiple level tab oriented interconnect architecture |
| 06/13/2002 | US20020070755 Registered logic macrocell with product term allocation and adjacent product term stealing |