Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
10/2002
10/02/2002CN1372383A Wire connection pad circuit and automatic gain regulation method used on it
10/02/2002CN1091974C Boosting pulse generation circuit
10/01/2002US6460148 Enhanced embedded logic analyzer
10/01/2002US6460134 Method and apparatus for a late pipeline enhanced floating point unit
10/01/2002US6460131 FPGA input output buffer with registered tristate enable
10/01/2002US6459556 Input buffer
10/01/2002US6459327 Feedback controlled substrate bias generator
10/01/2002US6459322 Level adjustment circuit and data output circuit thereof
10/01/2002US6459307 Input buffer having dual paths
10/01/2002US6459304 Latching annihilation based logic gate
10/01/2002US6459301 Semiconductor circuit device having active and standby states
10/01/2002US6459300 Level-shifting circuitry having “high” output during disable mode
10/01/2002US6459299 Tristate buffer
10/01/2002US6459298 Structure of controlled pipeline logic
10/01/2002US6459296 Method, system and method of using a component for setting the electrical characteristics of microelectronic circuit configurations
09/2002
09/26/2002WO2002075926A2 Antifuse reroute of dies
09/26/2002WO2002075534A1 Component/web service operational profile auto-sequencing
09/26/2002WO2001089091A3 Method and apparatus for incorporating a multiplier into an fpga
09/26/2002WO2001024466A9 Communication interface with terminated transmission lines
09/26/2002US20020138540 Multiplier circuit
09/26/2002US20020138530 Variable function information processor
09/26/2002US20020136340 Two-stage multiplier circuit
09/26/2002US20020135555 Single-ended high-voltage level shifter for a TFT-LCD gate driver
09/26/2002US20020135406 Controlled impedance driver receiving a combination binary and thermometer code
09/26/2002US20020135405 Push-pull output buffer with gate voltage feedback loop
09/26/2002US20020135404 High speed voltage mode differential digital output driver with edge-emphasis and pre-equalization
09/26/2002US20020135403 Trigger circuit
09/26/2002US20020135401 Input circuit
09/26/2002US20020135398 Integrated circuit devices having power control logic that inhibits internal leakage current loss during sleep mode operation and method of operating same
09/26/2002US20020135397 Semiconductor integrated circuits with power reduction mechanism
09/26/2002US20020135396 Circuit for receiving and driving a clock-signal
09/25/2002EP1243109A1 An arrangement for reducing power dissipation in a line driver
09/25/2002EP1243073A1 Circuitry and method for removing glitches in digital circuits
09/25/2002EP1088276B1 Interface module with protection circuit and method of protecting an interface
09/25/2002EP0960478B1 High-voltage cmos level shifter
09/25/2002CN1371175A Command input circuit with command acquisition unit
09/24/2002US6456559 Semiconductor integrated circuit
09/24/2002US6456553 Circuit configuration for switching over a receiver circuit in particular in DRAM memories and DRAM memory having the circuit configuration
09/24/2002US6456541 Booster circuit for raising voltage by sequentially transferring charges from input terminals of booster units to output terminals thereof in response to clock signals having different phases
09/24/2002US6456170 Comparator and voltage controlled oscillator circuit
09/24/2002US6456157 Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
09/24/2002US6456152 Charge pump with improved reliability
09/24/2002US6456150 Circuit for biasing a bulk terminal of a MOS transistor
09/24/2002US6456147 Output interface circuit
09/24/2002US6456139 Auto-detection and auto-enable of compact PCI bus pull-ups
09/24/2002US6456138 Method and apparatus for a single upset (SEU) tolerant clock splitter
09/24/2002US6456122 Input buffer circuit for transforming pseudo differential signals into full differential signals
09/24/2002US6456116 Dynamic comparator circuit
09/24/2002US6456115 Clock gate buffering circuit
09/24/2002US6456114 Power conserving CMOS semiconductor integrated circuit
09/24/2002US6456112 Method and apparatus for improving signal noise immunity in CMOS dynamic logic circuitry
09/24/2002US6456110 Voltage level shifter having zero DC current and state retention in drowsy mode
09/24/2002US6456108 Input circuit for an output stage
09/24/2002US6456107 CMOS-microprocessor chip and package anti-resonance method
09/24/2002US6455901 Semiconductor integrated circuit
09/19/2002WO2002073912A2 Line driver with slew-rate control
09/19/2002WO2002073805A1 A current mode device and a communication arrangement comprising current mode devices
09/19/2002WO2002073804A2 Line driver with current source output and high immunity to rf signals
09/19/2002WO2002029545A3 Asynchronously controlling data transfers within a circuit
09/19/2002WO2002001719A3 Method and apparatus for testing high performance circuits
09/19/2002US20020133752 Component/web service operational profile auto-sequencing
09/19/2002US20020133650 Boundary scannable one bit precompensated cmos driver with compensating pulse width control
09/19/2002US20020131314 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
09/19/2002US20020131298 Evaluation of conduction at precharged node
09/19/2002US20020131287 Power converter with increased breakdown voltage maintaining stable operation
09/19/2002US20020130692 Current-controlled CMOS logic family
09/19/2002US20020130690 Programmable dual drive strength output buffer with a shared boot circuit
09/19/2002US20020130688 Current mode device and an arrangement
09/19/2002US20020130687 Antifuse reroute of dies
09/19/2002US20020130686 CMOS gate array with vertical transistors
09/19/2002US20020130685 Monotonic dynamic static pseudo-NMOS logic circuits
09/19/2002US20020130684 CMOS output amplifier independent of temperature, supply voltage and manufacturing quality of transistors
09/19/2002US20020130683 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them
09/19/2002US20020130682 Adaptive threshold logic circuit
09/19/2002US20020130681 Programmable logic array integrated circuits
09/19/2002US20020130680 Method and apparatus for terminating emitter coupled logic (ECL) transceivers
09/19/2002DE10201890A1 Schaltung und Verfahren zur Kompensation eines Hochfrequenzsignalverlustes auf einer Übertragungsleitung Circuit and method for compensating a high-frequency signal loss on a transmission line
09/19/2002DE10111634A1 Electric compensation circuit for signal transit time influencing of integrated CMOS circuits, or chips
09/18/2002EP1240054A1 Circuit for activating a can (car area network) bus control unit
09/18/2002EP1078461B1 Circuit with individual electron components and method for the operation thereof
09/18/2002CN1370304A Integrated circuit and circuit arrangement for supplying intergrated circuit with electricity
09/18/2002CN1369968A Pre-setting circuit for n-trap bias voltage of CMOS circuit and its method
09/17/2002US6452856 DRAM technology compatible processor/memory chips
09/17/2002US6452827 I/O circuit of semiconductor integrated device
09/17/2002US6452442 Apparatus for obtaining noise immunity in electrical circuits
09/17/2002US6452429 High speed input buffer circuit for low voltage interface
09/17/2002US6452422 Interface circuit and operating method thereof
09/17/2002US6452418 Level shifter with independent grounds and improved EME-isolation
09/17/2002US6452417 I/O cell architecture for CPLDs
09/17/2002US6452365 Power converter with increased breakdown voltage maintaining stable operation
09/17/2002US6452259 Stacked substrate and semiconductor device
09/12/2002WO2002071612A2 Sub-micron high input voltage tolerant input output (i/o) circuit which accommodates large power supply variations
09/12/2002WO2002071611A2 Monotonic dynamic-static pseudo-nmos logic circuit and method of forming a logic gate array
09/12/2002WO2002071249A2 Method and devices for treating and/or processing data
09/12/2002WO2002071209A2 Evolutionary programming of configurable logic devices
09/12/2002WO2002071196A2 Methods and devices for treating and processing data
09/12/2002WO2001016708A9 System and method for detecting buffer overflow attacks
09/12/2002US20020129286 Microcomputer
09/12/2002US20020129077 High speed low power 4-2 compressor
09/12/2002US20020128812 Time-multiplexing data between asynchronous clock domains within cycle simulation and emulation environments
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