Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
12/2002
12/05/2002US20020183953 Method of fault isolation of a digital electronic device
12/05/2002US20020181641 Integrated circuit arrangement with feature control
12/05/2002US20020181558 Simultaneous plural code series generator and CDMA radio receiver using same
12/05/2002US20020180722 Signal processing circuit, low-voltage signal generator, and image display incorporating the same
12/05/2002US20020180513 Metal oxide semiconductor transistor circuit and semiconductor integrated circuit using the same
12/05/2002US20020180508 Semiconductor device
12/05/2002US20020180506 Supply voltage compensation circuit for high speed LVDS predrive
12/05/2002US20020180495 CMOS output circuit
12/05/2002US20020180494 Voltage level converting circuit
12/05/2002US20020180486 Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit
12/05/2002US20020180485 Dynamic semiconductor integrated circuit
12/05/2002US20020180484 Semiconductor integrated circuit
12/05/2002US20020180483 Variable voltage data buffers
12/05/2002US20020180481 Interface
12/05/2002US20020180480 Method and apparatus for inteface signaling using single-ended and differential data signals
12/05/2002US20020180479 Pull-up terminator
12/05/2002US20020179940 Semiconductor integrated circuit device with reduced leakage current
12/05/2002DE10211891A1 Intgrierte Halbleiterschaltung Intgrierte semiconductor circuit
12/04/2002EP1263142A1 Level shifter
12/04/2002EP1263047A2 Layout technique for C3MOS inductive broadbanding
12/04/2002EP1262903A2 Parallel signal processing circuit, semiconductor device having the circuit, and signal processing system having the circuit
12/04/2002EP1262021A1 Security switching device and a system of security switching devices
12/04/2002CN2524430Y Voltage/current conversion circuit
12/03/2002US6490714 Apparatus and method for in-system programming of a field programmable logic device using device-specific characterization data
12/03/2002US6489837 Digitally controlled impedance for I/O of an integrated circuit device
12/03/2002US6489833 Semiconductor integrated circuit device
12/03/2002US6489830 Apparatus and method for implementing a multiplexer
12/03/2002US6489815 Low-noise buffer circuit that suppresses current variation
12/03/2002US6489811 Logic gate with symmetrical propagation delay from any input to any output and a controlled output pulse width
12/03/2002US6489809 Circuit for receiving and driving a clock-signal
12/03/2002US6489808 Buffer circuit capable of carrying out interface with a high speed
12/03/2002US6489807 Output buffer and method of driving
12/03/2002US6489806 Zero-power logic cell for use in programmable logic devices
12/03/2002US6489804 Method for coupling logic blocks using low threshold pass transistors
11/2002
11/28/2002WO2002095942A2 Dual-edge triggered dynamic logic
11/28/2002WO2002095598A2 Programmable logic device including programmable interface core and central processing unit
11/28/2002WO2002095531A2 Circuit having a controllable slew rate
11/28/2002US20020178431 Configurable logic block with and gate for efficient multiplication in FPGAS
11/28/2002US20020178396 Systems and methods for providing automated diagnostic services for a cluster computer system
11/28/2002US20020178311 Quantized queue length arbiter
11/28/2002US20020176314 Dram technology compatible processor/memory chips
11/28/2002US20020176313 Dram technology compatible processor/memory chips
11/28/2002US20020176293 DRAM technology compatible processor/memory chips
11/28/2002US20020176288 Semiconductor integrated circuit device and test method thereof
11/28/2002US20020176285 Circut having a controllable slew rate
11/28/2002US20020175746 Semiconductor integrated circuit device
11/28/2002US20020175743 Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
11/28/2002US20020175741 Device and method for limiting the extent to which circuits in integrated circuit dice electrically load bond pads and other circuit nodes in the dice
11/28/2002US20020175734 Input/output circuit of semiconductor integrated circuit
11/28/2002US20020175717 Differential SCSI driver rise time and amplitude control circuit
11/28/2002US20020175713 Logic architecture for single event upset immunity
11/28/2002US20020175712 CMOS skewed static logic and method of synthesis
11/28/2002US20020175711 Methodology for improving noise immunity on logic circuits
11/28/2002US20020175710 Reverse biasing logic circuit
11/28/2002US20020175709 Universal single-ended parallel bus
11/28/2002US20020175708 Input/output interfacing circuit, input/output interface, and semiconductor device having input/out interfacing circuit
11/28/2002US20020175706 Level shift circuit
11/28/2002US20020175704 Double data rate flip-flop
11/28/2002US20020175703 Concurrent logic operations using decoder circuitry of a look-up table
11/28/2002US20020175701 Signal transmitting device suited to fast signal transmission
11/28/2002US20020175700 Impedance adjustment circuit
11/27/2002EP1261134A2 Digital phase locked loop
11/27/2002EP1261133A2 System and method for asymmetric routing lines
11/27/2002EP1163725B1 Fpga configurable logic block with multi-purpose logic/memory circuit
11/27/2002CN1381948A 半导体集成电路 The semiconductor integrated circuit
11/27/2002CN1381947A 半导体集成电路 The semiconductor integrated circuit
11/27/2002CN1095247C 输出电路 Output circuit
11/26/2002US6487136 Semiconductor memory device with reduced current consumption in data hold mode
11/26/2002US6486756 Superconductor signal amplifier
11/26/2002US6486709 Distributing data to multiple destinations within an asynchronous circuit
11/26/2002US6486708 Logic circuit and its forming method
11/26/2002US6486707 CMOS pass transistor logic circuitry using quantum mechanical tunneling structures
11/26/2002US6486706 Domino logic with low-threshold NMOS pull-up
11/26/2002US6486705 Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units
11/26/2002US6486704 Programmable burst FIFO
11/26/2002US6486702 Embedded memory blocks for programmable logic
11/26/2002US6486701 CPLD high speed path
11/26/2002US6486700 One-hot Muller C-elements and circuits using one-hot Muller C-elements
11/26/2002US6486699 Compensation circuit for driver circuits
11/26/2002US6486698 LSI device capable of adjusting the output impedance to match the characteristic impedance
11/26/2002US6486694 Universal delay-insensitive logic cell
11/26/2002US6486572 Semiconductor integrated circuit device with a stable operating internal circuit
11/26/2002US6486027 Field programmable logic arrays with vertical transistors
11/26/2002CA2074145C Compact fail safe interface and voting module comprising it
11/21/2002WO2002093746A1 Logic circuit with single event upset immunity
11/21/2002WO2002093745A2 Reconfigurable logic device
11/21/2002WO2002093404A2 Computing system
11/21/2002WO2002093341A2 Method and apparatus for controlling current demand in an integrated circuit
11/21/2002WO2002082653A3 Integrated circuit
11/21/2002US20020174373 Data transmission system using a pair of complementary signals as an edge-aligned strobe signal and input/output buffers therein
11/21/2002US20020173298 Wireless programmable logic devices
11/21/2002US20020172089 Dram technology compatible processor/memory chips
11/21/2002US20020172066 Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting
11/21/2002US20020171468 Apparatus for biasing ultra-low voltage logic circuits
11/21/2002US20020171466 Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation
11/21/2002US20020171453 Differential amplifier circuit capable of accurately amplifying even high-speeded signal of small amplitude
11/21/2002US20020171407 Method and apparatus for controlling current demand in an integrated circuit
11/21/2002US20020171095 Layout technique for C3MOS inductive broadbanding
11/21/2002DE10120790A1 Schaltungsanordnung zur Verringerung der Versorgungsspannung eines Schaltungsteils sowie Verfahren zum Aktivieren eines Schaltungsteils Circuit arrangement for reducing the supply voltage of a circuit part as well as methods for activating a circuit part
11/20/2002EP1258796A2 Copy protection method and system for a field-programmable gate array