| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 01/07/2003 | US6505337 Method for implementing large multiplexers with FPGA lookup tables |
| 01/07/2003 | US6504418 Using thick-oxide CMOS devices to interface high voltage integrated circuits |
| 01/07/2003 | US6504413 Buffer improvement |
| 01/07/2003 | US6504404 Semiconductor integrated circuit |
| 01/07/2003 | US6504402 Semiconductor integrated circuit device having power reduction mechanism |
| 01/07/2003 | US6504401 Configurable bus hold circuit with low leakage current |
| 01/07/2003 | US6504400 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit |
| 01/07/2003 | US6504399 Method and apparatus for universal program controlled bus architecture |
| 01/07/2003 | US6504397 Output controlled line driver with programmable common mode control |
| 01/03/2003 | WO2003001396A1 System and method for web server with a reconfigurable processor operating under single operation system image |
| 01/03/2003 | WO2003001351A2 METHOD FOR SMOOTHING dI/dT NOISE DUE TO CLOCK TRANSITIONS |
| 01/03/2003 | WO2001069837A3 Clock data recovery circuitry associated with programmable logic device circuitry |
| 01/02/2003 | US20030005402 System for simplifying the programmable memory to logic interface in FPGA |
| 01/02/2003 | US20030001674 Low-voltage, broadband operational amplifier |
| 01/02/2003 | US20030001663 Method and apparatus for dynamic leakage control |
| 01/02/2003 | US20030001661 Programmable reference voltage generating circuit |
| 01/02/2003 | US20030001658 Semiconductor device |
| 01/02/2003 | US20030001655 Level shifter |
| 01/02/2003 | US20030001646 Current-controlled CMOS logic family |
| 01/02/2003 | US20030001645 Input pad with improved noise immunity and output characteristics |
| 01/02/2003 | US20030001642 Low skew, power sequence independent cmos receiver device |
| 01/02/2003 | US20030001629 Signal transmission circuit capable of tolerating high-voltage input signal |
| 01/02/2003 | US20030001623 Conditional burn-in keeper for dynamic circuits |
| 01/02/2003 | US20030001622 Symmetric differential domino "AND gate" |
| 01/02/2003 | US20030001620 MOS-type semiconductor integrated circuit |
| 01/02/2003 | US20030001619 Semiconductor integrated circuit |
| 01/02/2003 | US20030001616 Level shifter and electro-optical apparatus incorporating the same |
| 01/02/2003 | US20030001615 Programmable logic circuit device having look up table enabling to reduce implementation area |
| 01/02/2003 | US20030001614 Field programmable logic device with efficient memory utilization |
| 01/02/2003 | US20030001613 Function block |
| 01/02/2003 | US20030001611 Driver impedance control mechanism |
| 01/02/2003 | US20030001610 Bus termination scheme for flexible uni-processor and dual processor platforms |
| 01/02/2003 | US20030001609 Circuit for improving noise immunity by DV/DT boosting |
| 01/02/2003 | US20030001184 Dynamic bus repeater with improved noise tolerance |
| 01/02/2003 | EP1271785A1 Noise-resistive, burst-mode receiving apparatus and method for recovering clock signal and data therefrom |
| 01/02/2003 | EP1271784A2 PLD architecture for flexible placement of IP function blocks |
| 01/02/2003 | EP1271783A2 FPGA with a simplified interface between the program memory and the programmable logic blocks |
| 01/02/2003 | EP1271782A2 FPGA with at least two different and independently configurable memory structures |
| 01/02/2003 | EP1271474A1 Function block |
| 01/02/2003 | EP1271290A2 Cold clock power reduction |
| 01/02/2003 | EP1269630A2 Current-controlled cmos circuits with inductive broadbanding |
| 01/02/2003 | EP0829139B1 A multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices |
| 01/02/2003 | DE10144384C1 Magnetic logic module used as inverter has magnetic field sensor supplied with read signal for providing output signal which is inverted relative to input signal |
| 01/01/2003 | CN2529453Y Output buffer with reducing noise of source/grounded bounce device |
| 01/01/2003 | CN1388501A Pulse output circuit, shift register and display device |
| 12/31/2002 | US6502208 Method and system for check stop error handling |
| 12/31/2002 | US6502119 High speed microprocessor zero detection circuit with 32-bit and 64-bit modes |
| 12/31/2002 | US6501677 Configuration memory architecture for FPGA |
| 12/31/2002 | US6501407 Digital to analog converter |
| 12/31/2002 | US6501400 Correction of operational amplifier gain error in pipelined analog to digital converters |
| 12/31/2002 | US6501326 Semiconductor integrated circuit |
| 12/31/2002 | US6501323 Voltage switching circuit |
| 12/31/2002 | US6501321 Level shift circuit |
| 12/31/2002 | US6501318 High speed input buffer circuit |
| 12/31/2002 | US6501317 High speed, low-power CMOS circuit with constant output swing and variable time delay for a voltage controlled oscillator |
| 12/31/2002 | US6501309 Semiconductor device having timing stabilization circuit with overflow detection function |
| 12/31/2002 | US6501306 Data output circuit for semiconductor device with level shifter and method for outputting data using the same |
| 12/31/2002 | US6501301 Semiconductor integrated circuit and an electronic apparatus incorporating a multiplicity of semiconductor integrated circuits |
| 12/31/2002 | US6501300 Semiconductor integrated circuit |
| 12/31/2002 | US6501298 Level-shifting circuitry having “low” output during disable mode |
| 12/31/2002 | US6501296 Logic/memory circuit having a plurality of operating modes |
| 12/31/2002 | US6501295 Overdriven pass transistors |
| 12/31/2002 | US6501293 Method and apparatus for programmable active termination of input/output devices |
| 12/31/2002 | CA2089429C Low power noise rejecting ttl to cmos input buffer |
| 12/27/2002 | WO2002103909A1 Gain compensation and bias current control in an lvds circuit |
| 12/27/2002 | WO2002103907A1 Input pad with improved noise immunity and output characteristics |
| 12/27/2002 | WO2002103518A1 Efficient high performance data operation element for use in a reconfigurable logic environment |
| 12/26/2002 | US20020199135 Instructive demonstration method of a measuring device using a network, and system for the method |
| 12/26/2002 | US20020198607 Programmable controller with sub-phase clocking scheme |
| 12/26/2002 | US20020196809 Methods for configuring FPGA ' S having viriable grain components for providing time-shared access to interconnect resources |
| 12/26/2002 | US20020196673 Booster circuit for raising voltage by sequentially transferring charges from input terminals of booster units to output terminals thereof in response to clock signals having different phases |
| 12/26/2002 | US20020196075 Method for smoothing di/dt noise due to clock transitions |
| 12/26/2002 | US20020196068 A Bus Agent Utilizing Dynamic Biasing Circuitry to Translate a Signal to a Core Voltage Level |
| 12/26/2002 | US20020196059 Memory system including a memory device having a controlled output driver characteristic |
| 12/26/2002 | US20020196058 Low-amplitude driver circuit |
| 12/26/2002 | US20020196057 Data output circuit with reduced output noise |
| 12/26/2002 | US20020196053 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit |
| 12/26/2002 | US20020196051 MOS-type semiconductor integrated circuit |
| 12/26/2002 | US20020196049 LSI device capable of adjusting the output impedance to match the characteristic impedance |
| 12/26/2002 | US20020196035 Digitally controlled adaptive driver for sensing capacitive load |
| 12/26/2002 | US20020195649 Field programmable logic arrays with vertical transistors |
| 12/26/2002 | US20020195648 Semiconductor device having an ESD protective circuit |
| 12/25/2002 | CN1387319A NOT gate circuit structure |
| 12/25/2002 | CN1387318A Over-voltage protector circuit with output buffer |
| 12/25/2002 | CN1387177A Signal processing circuit, low voltage signal generator and picture display provided with them |
| 12/25/2002 | CN1097344C CMOS driver circuit |
| 12/25/2002 | CN1097343C Interface circuit and method of setting determination level therefor |
| 12/25/2002 | CA2391798A1 Function block |
| 12/24/2002 | US6498817 Circuit for processing data signals |
| 12/24/2002 | US6498762 Semiconductor integrated circuit device and method of activating the same |
| 12/24/2002 | US6498760 Semiconductor device having test mode |
| 12/24/2002 | US6498744 Ferroelectric data processing device |
| 12/24/2002 | US6498738 Reverse level shift circuit and power semiconductor device |
| 12/24/2002 | US6498520 Minimizing the effect of clock skew in precharge circuit |
| 12/24/2002 | US6498518 Low input impedance line/bus receiver |
| 12/24/2002 | US6498515 Semiconductor integrated circuit and method for designing the same |
| 12/24/2002 | US6498514 Domino circuit |
| 12/24/2002 | US6498510 Adaptive threshold logic circuit |
| 12/24/2002 | US6498508 Semiconductor integrated circuit device and testing method therefor |
| 12/24/2002 | US6498371 Body-tied-to-body SOI CMOS inverter circuit |