| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
|---|
| 08/08/2002 | US20020105041 Integrated circuit device with switching between active mode and standby mode controlled by digital circuit |
| 08/08/2002 | DE10105045A1 Überspannungsschutzschaltung mit Erfassung eines Überspannungsabbaus Overvoltage protection circuit with detection of an overvoltage breakdown |
| 08/07/2002 | EP1229652A2 Enhanced field programmable gate array |
| 08/07/2002 | EP1229651A2 Enhanced field programmable gate array |
| 08/07/2002 | EP1229650A2 Output circuit, input circuit and input/output circuit |
| 08/07/2002 | EP1229649A2 Output circuit, input circuit and input/output circuit |
| 08/07/2002 | EP1229648A2 Output circuit, input circuit and input/output circuit |
| 08/07/2002 | EP1229453A2 A field programmable processor |
| 08/07/2002 | CN1362743A Semicondcutor integrated circuit |
| 08/07/2002 | CN1088943C breakdown protection circuit using high voltage detection |
| 08/07/2002 | CN1088942C Output buffer circuit having low noise characteristics |
| 08/06/2002 | US6430606 High speed signaling for interfacing VLSI CMOS circuits |
| 08/06/2002 | US6430585 Noise tolerant conductance-based logic gate and methods of operation and manufacturing thereof |
| 08/06/2002 | US6430102 Semiconductor integrated circuit and method for controlling activation thereof |
| 08/06/2002 | US6429743 Signal conversion circuit for stable differential amplification and semiconductor device provided with the same as input buffer |
| 08/06/2002 | US6429717 Receiving circuit |
| 08/06/2002 | US6429716 Pre-buffer voltage level shifting circuit and method |
| 08/06/2002 | US6429708 Signal output device and method for sending signals at multiple transfer rates while minimizing crosstalk effects |
| 08/06/2002 | US6429704 Power consumption reduction method, power consumption reduction circuit, control circuit, and hard disk drive apparatus |
| 08/06/2002 | US6429691 Differential-input circuit |
| 08/06/2002 | US6429689 Method and apparatus for controlling both active and standby power in domino circuits |
| 08/06/2002 | US6429688 Semiconductor integrated circuit |
| 08/06/2002 | US6429687 Semiconductor integrated circuit device |
| 08/06/2002 | US6429686 Output driver circuit using thin and thick gate oxides |
| 08/06/2002 | US6429685 Integrated circuit and method of controlling output impedance |
| 08/06/2002 | US6429684 Circuit having dynamic threshold voltage |
| 08/06/2002 | US6429683 Low-power CMOS digital voltage level shifter |
| 08/06/2002 | US6429681 Programmable logic device routing architecture to facilitate register re-timing |
| 08/06/2002 | US6429680 Pin programmable reference |
| 08/06/2002 | US6429679 Programmable impedance control circuit and method thereof |
| 08/06/2002 | US6429492 Low-power CMOS device and logic gates/circuits therewith |
| 08/01/2002 | WO2002060061A2 Domino logic with self-timed precharge |
| 08/01/2002 | WO2002060042A1 Voltage conversion circuit and semiconductor integrated circuit device provided with it |
| 08/01/2002 | WO2002059979A1 Semiconductor device |
| 08/01/2002 | WO2002059759A2 Spatially filtered data bus drivers and receivers and method of operating same |
| 08/01/2002 | WO2002045267A9 Circuit for receiving and driving a clock-signal |
| 08/01/2002 | WO2002013389A3 An interconnection network for a field programmable gate array |
| 08/01/2002 | US20020101777 Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox |
| 08/01/2002 | US20020101278 Digitally controlled impedance for I/O of an integrated circuit device |
| 08/01/2002 | US20020101274 Voltage level translator systems and methods |
| 08/01/2002 | US20020101272 Input-output buffer circuit and method for avoiding inadvertent conduction of a pull-up transistor |
| 08/01/2002 | US20020101266 High bandwidth clock buffer |
| 08/01/2002 | US20020101265 Method and apparatus for a low power, multi-mode GTL I/O buffer utilizing midrail I/O buffer pad clamping |
| 08/01/2002 | US20020101262 Logical circuit |
| 08/01/2002 | US20020101259 Interconnect circuitry for implementing logic functions in a field programmable gate array and method of operation |
| 08/01/2002 | US20020101258 Architecture and interconnect scheme for programmable logic circuits |
| 08/01/2002 | US20020101257 Semiconductor device |
| 08/01/2002 | US20020101249 Semiconductor integrated circuit and method for testing the same |
| 08/01/2002 | DE10060662C1 Leitungstreiberanordnung Line driver arrangement |
| 08/01/2002 | DE10049629C1 Programmable circuit has sub-networks alternately formed in microchip common plane so logic blocks of one lie in gaps in another; sub-networks are connected at network edges |
| 07/31/2002 | EP1226526A2 An emulation system having a efficient emulation signal routing architecture |
| 07/31/2002 | EP1038355B1 Buffer circuit |
| 07/31/2002 | EP1010053B1 Interface circuit for full-custom and semi-custom timing domains |
| 07/31/2002 | CN1361944A Tristate circuit for power up conditions |
| 07/30/2002 | US6427156 Configurable logic block with AND gate for efficient multiplication in FPGAS |
| 07/30/2002 | US6426908 Semiconductor memory device with reduced current consumption in data hold mode |
| 07/30/2002 | US6426854 Voltage clamp |
| 07/30/2002 | US6426661 Clock distribution with constant delay clock buffer circuit |
| 07/30/2002 | US6426658 Buffers with reduced voltage input/output signals |
| 07/30/2002 | US6426654 Signal transmission circuit on semiconductor integrated circuit chip |
| 07/30/2002 | US6426653 MOS output driver, and circuit and method of controlling same |
| 07/30/2002 | US6426652 Dual-edge triggered dynamic logic |
| 07/30/2002 | US6426651 Method and apparatus for improving the performance of buffers using a translator circuit |
| 07/30/2002 | US6426650 Integrated circuit with metal programmable logic having enhanced reliability |
| 07/30/2002 | US6426649 Architecture for field programmable gate array |
| 07/30/2002 | US6426648 Carry lookahead for programmable logic array |
| 07/30/2002 | US6426647 Dual rail drive for distributed logic |
| 07/30/2002 | US6426646 ECL terminating circuit |
| 07/30/2002 | US6426645 Semiconductor device that fixes a potential on an input signal wiring |
| 07/30/2002 | US6426261 Logic circuit and its fabrication method |
| 07/25/2002 | WO2002058241A2 Method for conditioning semiconductor-on-insulator transsistors in programmable logic devices |
| 07/25/2002 | WO2002058240A1 Self-terminating current mirror transceiver logic |
| 07/25/2002 | WO2001001575A9 System memory access system and method for reconfigurable chip |
| 07/25/2002 | US20020099969 Data input and output device using timer function |
| 07/25/2002 | US20020097682 Low frequency loop-back in a high speed optical transceiver |
| 07/25/2002 | US20020097606 Semiconductor circuit |
| 07/25/2002 | US20020097212 Display device having an improved voltage level converter circuit |
| 07/25/2002 | US20020097071 Output buffer with constant switching current |
| 07/25/2002 | US20020097069 Domino logic with self-timed precharge |
| 07/25/2002 | US20020097068 System and method for improving signal propagation |
| 07/25/2002 | US20020097067 Ground bounce detection circuit for use in data error reduction |
| 07/25/2002 | US20020096740 Logic apparatus and logic circuit |
| 07/25/2002 | US20020096677 Semiconductor integrated circuit having noise detect circuits detecting noise on power supply nets |
| 07/25/2002 | DE10200859A1 System und Verfahren zum Steuern von Verzögerungszeiten bei Floating-Body-Cmosfet-Invertern System and method for controlling delay times for floating body CMOSFET inverters |
| 07/24/2002 | EP1224737A1 Heterogeneous interconnection architecture for programmable logic devices |
| 07/24/2002 | EP1224736A1 Push-pull end stage for digital signals with controlled output levels |
| 07/24/2002 | EP1224481A1 Apparatus and method for programmable parametric toggle testing of digital cmos pads |
| 07/24/2002 | CN1360758A Cascode signal driver with low harmonic content |
| 07/24/2002 | CN1360757A Circuit arrangement for generating current impulses in supply current of integrated circuits |
| 07/23/2002 | US6425097 Method and apparatus for testing an impedance-controlled input/output (I/O) buffer in a highly efficient manner |
| 07/23/2002 | US6425068 Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas) |
| 07/23/2002 | US6424957 Method and apparatus for parallel processing of fuzzy rules |
| 07/23/2002 | US6424586 Semiconductor integrated circuit device and method of activating same |
| 07/23/2002 | US6424567 Fast reconfigurable programmable device |
| 07/23/2002 | US6424509 Semiconductor including a protective circuit |
| 07/23/2002 | US6424217 CMOS low-voltage PECL driver with initial current boost |
| 07/23/2002 | US6424206 Input circuit and output circuit |
| 07/23/2002 | US6424194 Current-controlled CMOS logic family |
| 07/23/2002 | US6424188 Signal transmission device |
| 07/23/2002 | US6424186 Circuit for dynamic signal drive strength compensation |