Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
11/2002
11/20/2002EP1257928A2 Reconfigurable logic for a computer
11/20/2002CN1380660A 控制电路和半导体存储器装置 The control circuit and semiconductor memory device
11/20/2002CN1094681C High-quality dynamic comparision circuit and reading amplifier circuit
11/20/2002CN1094680C Serial-type nixie tube decoding circuit
11/20/2002CN1094679C 半导体器件 Semiconductor devices
11/20/2002CN1094613C Interface circuit and method for low power loss transfer binary logic signals
11/19/2002US6483886 Phase-locked loop circuitry for programmable logic devices
11/19/2002US6483375 Low power operation mechanism and method
11/19/2002US6483373 Input circuit having signature circuits in parallel in semiconductor device
11/19/2002US6483366 Breakdown-free negative level shifter
11/19/2002US6483354 PCI-X driver control
11/19/2002US6483349 Semiconductor integrated circuit device
11/19/2002US6483348 Reducing power consumption variability of static busses
11/19/2002US6483347 High speed digital signal buffer and method
11/19/2002US6483346 Failsafe interface circuit with extended drain services
11/19/2002US6483345 High speed level shift circuit for low voltage output
11/19/2002US6483344 Interconnect circuitry for implementing logic functions in a field programmable gate array and method of operation
11/19/2002US6483343 Configurable computational unit embedded in a programmable device
11/19/2002US6483342 Multi-master multi-slave system bus in a field programmable gate array (FPGA)
11/19/2002US6483340 High integration-capable output buffer circuit unaffected by manufacturing process fluctuations or changes in use
11/19/2002US6483339 Single flux quantum series biasing technique using superconducting DC transformer
11/19/2002US6483165 Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation
11/14/2002WO2002091583A1 Modified repetitive cell matching technique for integrated circuits
11/14/2002WO2002091577A2 Clock noise reduction method and apparatus
11/14/2002WO2001022591A9 Two-stage muller c-element
11/14/2002US20020170014 Apparatus and method to facilitate self-correcting memory
11/14/2002US20020169079 Rapid single-flux-quantum logic circuit and rapid single-flux-quantum output conversion circuit
11/14/2002US20020168067 Copy protection method and system for a field-programmable gate array
11/14/2002US20020168024 Digital line driver circuit
11/14/2002US20020167435 Modified repetitive cell matching technique for integrated circuits
11/14/2002US20020167339 Data comparator using non-inverting and inverting strobe signals as a dynamic reference voltage and input buffer using the same
11/14/2002US20020167338 Signal transfer circuit
11/14/2002US20020167335 Low power dynamic logic circuit
11/14/2002US20020167334 Semiconductor integrated circuit
11/14/2002US20020167333 Differential signal output circuit
11/14/2002US20020167026 Pulse output circuit, shift register and display device
11/13/2002EP1257102A1 Digital line driver circuit operable with and without pre-emphasis
11/13/2002EP1256081A1 Method and circuit for providing interface signals between integrated circuits
11/13/2002EP1256075A1 Supporting multiple fpga configuration modes using dedicated on-chip processor
11/13/2002CN1094268C 低压工作的触发器电路 Low-voltage operation of the flip-flop circuit
11/12/2002US6480974 Method for use of bus parking states to communicate diagnostic information
11/12/2002US6480954 Method of time multiplexing a programmable logic device
11/12/2002US6480937 Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--
11/12/2002US6480798 Method and apparatus for independent output driver calibration
11/12/2002US6480136 Modified repetitive cell matching technique for integrated circuits
11/12/2002US6480055 Decoder element for generating an output signal having three different potentials and an operating method for the decoder element
11/12/2002US6480054 Digital electronic circuit for use in implementing digital logic functions
11/12/2002US6480050 Level shifter with no quiescent DC current flow
11/12/2002US6480048 Circuit for generating an inverse signal of a digital signal with a minimal delay difference between the inverse signal and the digital signal
11/12/2002US6480039 Input buffer of an integrated semiconductor circuit
11/12/2002US6480034 MOS-type semiconductor integrated circuit
11/12/2002US6480030 Bus configuration and input/output buffer
11/12/2002US6480029 Three-volt TIA/EIA-485 driver circuit
11/12/2002US6480028 Programmable logic device architectures with super-regions having logic regions and memory region
11/12/2002US6480027 Driver circuitry for programmable logic devices
11/12/2002US6480026 Multi-functional I/O buffers in a field programmable gate array (FPGA)
11/12/2002US6480025 Driver circuitry for programmable logic devices with hierarchical interconnection resources
11/12/2002US6480023 Configurable logic block for PLD
11/12/2002US6480022 Low voltage differential dual receiver
11/12/2002US6480021 Transmitter circuit comprising timing deskewing means
11/12/2002CA2214306C Mos systems and methods of use
11/12/2002CA2199902C Interface circuit and method for transmitting binary logic signals with reduced power dissipation
11/12/2002CA2115169C Vehicle light, windshield wiper control system
11/07/2002WO2002089329A2 Fpga logic element with variable-length shift register capability
11/07/2002WO2002089133A2 Data integrity error handling in a redundant storage array
11/07/2002US20020166106 System and method for asymmetric routing lines
11/07/2002US20020166003 Method and apparatus for a failure-free synchronizer
11/07/2002US20020163845 Semiconductor device with reduced current consumption in standby state
11/07/2002US20020163841 Voltage-level shifter and semiconductor memory using the same
11/07/2002US20020163456 Reducing jitter in mixed-signal integrated circuit devices
11/07/2002US20020163365 Semiconductor integrated circuit device with voltage interface circuit
11/07/2002US20020163364 Power supply detection device
11/07/2002US20020163362 Race logic circuit
11/07/2002US20020163360 Constant impedance driver for high speed interface
11/07/2002US20020163359 Data transformation for the reduction of power and noise in CMOS structures
11/07/2002US20020163358 Use of dangling partial lines for interfacing in a PLD
11/07/2002US20020163357 Architecture and interconnect scheme for programmable logic circuits
11/07/2002US20020163356 PLD architecture for flexible placement of IP function blocks
11/07/2002US20020163355 Pad calibration circuit with on-chip resistor
11/07/2002US20020163354 Integrated circuit and associated design method using spare gate islands
11/07/2002DE10215763A1 System und Verfahren zum Verbessern der Leistungsfähigkeit von dynamischen Schaltungen System and method for improving the performance of dynamic circuits
11/06/2002EP1255255A2 High speed decoder for flash memory
11/06/2002EP0846372B1 Cmos buffer circuit having increased speed
11/06/2002EP0808026B1 Fail-safe timer circuit and on-delay circuit using the same
11/06/2002CN1378719A Multi-clock integrated circuit with clock generator and bi-directional clock pin arrangement
11/06/2002CN1378342A Insulator used for multiple power supply system
11/06/2002CN1378287A Complementary metal oxide semiconductor output circuit
11/05/2002US6477608 Interface circuit for transferring data on bus between modules of integrated circuit with reduced delay
11/05/2002US6477099 Integrated circuit with a differential amplifier
11/05/2002US6477092 Level shifter of nonvolatile semiconductor memory
11/05/2002US6476680 Cascode amplifying circuit and folded cascode amplifying circuit
11/05/2002US6476659 Voltage level shifter and phase splitter
11/05/2002US6476654 Slew rate adjusting circuit
11/05/2002US6476650 Method for outputting data and circuit configuration with driver circuit
11/05/2002US6476646 Sense amplifier of semiconductor integrated circuit
11/05/2002US6476645 Method and apparatus for mitigating the history effect in a silicon-on-insulator (SOI)-based circuit
11/05/2002US6476644 Clocked logic gate circuit
11/05/2002US6476642 Differential current driver circuit
11/05/2002US6476641 Low power consuming circuit
11/05/2002US6476640 Method for buffering an input signal
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