| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 01/31/2013 | US20130027113 Power Semiconductor Chip Having Two Metal Layers on One Face |
| 01/31/2013 | US20130027079 Field programmable gate array utilizing two-terminal non-volatile memory |
| 01/31/2013 | US20130026720 Electrostatic chuck |
| 01/31/2013 | US20130026693 Substrate supporting edge ring with coating for improved soak performance |
| 01/31/2013 | US20130026690 Wet-etching jig |
| 01/31/2013 | US20130026663 Method for curing defects in a semiconductor layer |
| 01/31/2013 | US20130026659 Microelectronic component |
| 01/31/2013 | US20130026658 Wafer level chip scale package for wire-bonding connection |
| 01/31/2013 | US20130026657 Semiconductor package and method of fabricating the same |
| 01/31/2013 | US20130026655 Chip package structure and method of manufacturing the same |
| 01/31/2013 | US20130026653 Method for manufacturing semiconductor device |
| 01/31/2013 | US20130026650 Semiconductor device, semiconductor module structure configured by vertically stacking semiconductor devices, and manufacturing method thereof |
| 01/31/2013 | US20130026649 Semiconductor device and manufacturing method therefor |
| 01/31/2013 | US20130026646 Passivated through wafer vias in low-doped semiconductor substrates |
| 01/31/2013 | US20130026645 Low stress vias |
| 01/31/2013 | US20130026644 Photoactive Compound Gradient Photoresist |
| 01/31/2013 | US20130026643 Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication |
| 01/31/2013 | US20130026642 Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad |
| 01/31/2013 | US20130026641 Conductor contact structure and forming method, and photomask pattern generating method for defining such conductor contact structure |
| 01/31/2013 | US20130026639 Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme |
| 01/31/2013 | US20130026638 Wafer-Level Chip Scale Package |
| 01/31/2013 | US20130026637 Metal gate electrode of a field effect transistor |
| 01/31/2013 | US20130026635 Hybrid Copper Interconnect Structure and Method of Fabricating Same |
| 01/31/2013 | US20130026634 Hybrid Interconnect Technology |
| 01/31/2013 | US20130026633 Multilayer Metallization with Stress-Reducing Interlayer |
| 01/31/2013 | US20130026631 Semiconductor apparatus and manufacturing method thereof |
| 01/31/2013 | US20130026630 Flip chips having multiple solder bump geometries |
| 01/31/2013 | US20130026629 Semiconductor device, semiconductor device unit, and semiconductor device production method |
| 01/31/2013 | US20130026628 Flip Chip Interconnection having Narrow Interconnection Sites on the Substrate |
| 01/31/2013 | US20130026627 Electronic chip comprising connection pillars and manufacturing method |
| 01/31/2013 | US20130026626 Method for forming bumps and substrate including the bumps |
| 01/31/2013 | US20130026624 Coaxial solder bump support structure |
| 01/31/2013 | US20130026623 Semiconductor Devices, Packaging Methods and Structures |
| 01/31/2013 | US20130026620 Self-aligning conductive bump structure and method of making the same |
| 01/31/2013 | US20130026618 Method and device for circuit routing by way of under-bump metallization |
| 01/31/2013 | US20130026617 Methods of forming a metal silicide region in an integrated circuit |
| 01/31/2013 | US20130026616 Power device package module and manufacturing method thereof |
| 01/31/2013 | US20130026615 Double-side exposed semiconductor device and its manufacturing method |
| 01/31/2013 | US20130026614 Structure and method for bump to landing trace ratio |
| 01/31/2013 | US20130026612 Method of shielding through silicon vias in a passive interposer |
| 01/31/2013 | US20130026610 Lithography method and device |
| 01/31/2013 | US20130026609 Package assembly including a semiconductor substrate with stress relief structure |
| 01/31/2013 | US20130026608 Process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate |
| 01/31/2013 | US20130026607 Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same |
| 01/31/2013 | US20130026606 Tsv pillar as an interconnecting structure |
| 01/31/2013 | US20130026605 WLCSP for Small, High Volume Die |
| 01/31/2013 | US20130026601 Semiconductor Device and Method for Manufacturing a Semiconductor |
| 01/31/2013 | US20130026600 Forming air gaps in memory arrays and memory arrays with air gaps thus formed |
| 01/31/2013 | US20130026590 Sloped structure, method for manufacturing sloped structure, and spectrum sensor |
| 01/31/2013 | US20130026582 Partial poly amorphization for channeling prevention |
| 01/31/2013 | US20130026579 Techniques Providing High-K Dielectric Metal Gate CMOS |
| 01/31/2013 | US20130026578 Semiconductor device and method of manufacturing the same |
| 01/31/2013 | US20130026576 Combined Output Buffer and ESD Diode Device |
| 01/31/2013 | US20130026575 Threshold adjustment of transistors by controlled s/d underlap |
| 01/31/2013 | US20130026574 Semiconductor device, method for manufacturing same, and display device |
| 01/31/2013 | US20130026573 Body contact soi transistor structure and method of making |
| 01/31/2013 | US20130026572 N-channel and p-channel finfet cell architecture |
| 01/31/2013 | US20130026571 N-channel and p-channel finfet cell architecture with inter-block insulator |
| 01/31/2013 | US20130026570 Borderless contact for ultra-thin body devices |
| 01/31/2013 | US20130026569 Methods and apparatus related to hot carrier injection reliability improvement |
| 01/31/2013 | US20130026568 Planar srfet using no additional masks and layout method |
| 01/31/2013 | US20130026567 Finfet drive strength modification |
| 01/31/2013 | US20130026565 Low rdson resistance ldmos |
| 01/31/2013 | US20130026562 Vertical memory cell |
| 01/31/2013 | US20130026559 Silicon-carbide mosfet cell structure and method for forming same |
| 01/31/2013 | US20130026558 Semiconductor devices including variable resistance material and methods of fabricating the same |
| 01/31/2013 | US20130026557 Sonos non-volatile memory cell and fabricating method thereof |
| 01/31/2013 | US20130026553 NVM Bitcell with a Replacement Control Gate and Additional Floating Gate |
| 01/31/2013 | US20130026552 Split-gate flash memory exhibiting reduced interference |
| 01/31/2013 | US20130026549 Semiconductor integrated circuit having capacitor for providing stable power and method of manufacturing the same |
| 01/31/2013 | US20130026546 Integrated circuit comprising an isolating trench and corresponding method |
| 01/31/2013 | US20130026545 Multiple well drain engineering for hv mos devices |
| 01/31/2013 | US20130026543 Semiconductor device and manufacturing method thereof |
| 01/31/2013 | US20130026540 Methods and apparatus for forming semiconductor structures |
| 01/31/2013 | US20130026539 Replacement source/drain finfet fabrication |
| 01/31/2013 | US20130026536 Insulated gate semiconductor device with optimized breakdown voltage, and manufacturing method thereof |
| 01/31/2013 | US20130026499 Wafer-level packaging for solid-state transducers and associated systems and methods |
| 01/31/2013 | US20130026497 Silicon carbide substrate manufacturing method and silicon carbide substrate |
| 01/31/2013 | US20130026496 Semiconductor Device and Manufacturing Method Thereof |
| 01/31/2013 | US20130026495 III-Nitride Metal Insulator Semiconductor Field effect Transistor |
| 01/31/2013 | US20130026492 Diamond Semiconductor System and Method |
| 01/31/2013 | US20130026490 Glass/ceramics replacement of epoxy for high temperature hermetically sealed non-axial electronic packages |
| 01/31/2013 | US20130026489 AlN BUFFER N-POLAR GaN HEMT PROFILE |
| 01/31/2013 | US20130026488 Epitaxial substrate and method for manufacturing epitaxial substrate |
| 01/31/2013 | US20130026486 Epitaxial substrate and method for manufacturing epitaxial substrate |
| 01/31/2013 | US20130026482 Boron-Containing Buffer Layer for Growing Gallium Nitride on Silicon |
| 01/31/2013 | US20130026480 Nucleation of Aluminum Nitride on a Silicon Substrate Using an Ammonia Preflow |
| 01/31/2013 | US20130026479 Semiconductor thin-film forming method, semiconductor device, semiconductor device manufacturing method, substrate, and thin-film substrate |
| 01/31/2013 | US20130026471 Circuit Structures, Memory Circuitry, And Methods |
| 01/31/2013 | US20130026466 Testing architecture of circuits integrated on a wafer |
| 01/31/2013 | US20130026465 Semiconductor device including an asymmetric feature, and method of making the same |
| 01/31/2013 | US20130026463 Electronic device and manufacturing method for same |
| 01/31/2013 | US20130026462 Method for manufacturing thin film transistor and thin film transistor manufactured by the same, and active matrix substrate |
| 01/31/2013 | US20130026450 Nitride-based heterojuction semiconductor device and method for the same |
| 01/31/2013 | US20130026449 Hybrid CMOS Technology with Nanowire Devices and Double Gated Planar Devices |
| 01/31/2013 | US20130026444 Synthesizing graphene from metal-carbon solutions using ion implantation |
| 01/31/2013 | US20130026443 Silicon nanowire comprising high density metal nanoclusters and method of preparing the same |
| 01/31/2013 | US20130026437 Resistance variable memory device and method for fabricating the same |
| 01/31/2013 | US20130026436 Phase change memory electrode with sheath for reduced programming current |
| 01/31/2013 | US20130026152 Pressurizing-type lamp annealing device, method for producing thin film, and method for using pressurizing-type lamp annealing device |