Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2013
02/07/2013WO2013016942A1 Multi-chamber semiconductor processing device
02/07/2013WO2013016941A1 Adjustable semiconductor processing device and control method thereof
02/07/2013WO2013016931A1 Masking method for deep etching based on buffer layer
02/07/2013WO2013016917A1 Method of manufacturing complementary metal-oxide-semiconductor field effect transistor
02/07/2013WO2013016853A1 Semiconductor device and method for manufacturing the same
02/07/2013WO2013016852A1 Method of fabricating semiconductor device
02/07/2013WO2013002502A9 Texture etchant composition for crystalline silicon wafer and texture etching method thereof
02/07/2013WO2012170302A3 Method for providing high etch rate
02/07/2013WO2012169731A3 Nand flash memory having 3-dimensional structure
02/07/2013WO2012165903A3 Semiconductor light-emitting device, method for manufacturing same, and semiconductor light-emitting device package and laser-processing apparatus comprising same
02/07/2013WO2012125681A4 Method to mitigate through-silicon via-induced substrate noise
02/07/2013WO2011046191A9 Jig for semiconductor production and method for producing same
02/07/2013US20130035498 Semiconductor that has a functionalized surface
02/07/2013US20130035021 Polishing pad, manufacturing method therefor, and method for manufacturing a semiconductor device
02/07/2013US20130035020 Versatile workpiece refining
02/07/2013US20130034970 Plasma processing method
02/07/2013US20130034969 Thin Film Deposition Method
02/07/2013US20130034968 Dry-etch for silicon-and-carbon-containing films
02/07/2013US20130034967 Gasket with positioning feature for clamped monolithic showerhead electrode
02/07/2013US20130034966 Chemical dispersion method and device
02/07/2013US20130034965 Methods of forming fine patterns using dry etch-back processes
02/07/2013US20130034964 Method for manufacturing a semiconductor device
02/07/2013US20130034963 Methods of forming fine patterns for semiconductor device
02/07/2013US20130034962 Method for Reducing a Minimum Line Width in a Spacer-Defined Double Patterning Process
02/07/2013US20130034961 Plasma Etching Method
02/07/2013US20130034960 Method of fabricating a semiconductor device
02/07/2013US20130034959 Electroless plating apparatus and method
02/07/2013US20130034958 Method of Fabricating an Integrated Device
02/07/2013US20130034957 Method of forming semiconductor device
02/07/2013US20130034956 Cleaning residual molding compound on solder bumps
02/07/2013US20130034955 Semiconductor device
02/07/2013US20130034954 Integrated circuit system including nitride layer technology
02/07/2013US20130034953 Cmos semiconductor device and method for manufacturing the same
02/07/2013US20130034952 Transistor structure having a trench drain
02/07/2013US20130034951 Method of manufacturing free-standing gallium nitride substrate
02/07/2013US20130034950 Method for fabricating p-type polycrystalline silicon-germanium structure
02/07/2013US20130034949 Method of forming trench isolation
02/07/2013US20130034948 Method of Manufacturing a Semiconductor Device
02/07/2013US20130034947 Atomic layer deposition of metal oxides for memory applications
02/07/2013US20130034946 Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors
02/07/2013US20130034945 Nonvolatile Memory Device and Method of Fabricating the Same
02/07/2013US20130034944 Method for making a disilicide
02/07/2013US20130034943 Tri-Gate Field-Effect Transistors Formed by Aspect Ration Trapping
02/07/2013US20130034942 High-k metal gate electrode structures formed by early cap layer adaptation
02/07/2013US20130034941 Forming sic mosfets with high channel mobility by treating the oxide interface with cesium ions
02/07/2013US20130034940 Low Threshold Voltage And Inversion Oxide thickness Scaling For A High-K Metal Gate P-Type MOSFET
02/07/2013US20130034939 Method of manufacturing power device
02/07/2013US20130034938 Replacement gate etsoi with sharp junction
02/07/2013US20130034937 Exposed Die Package for Direct Surface Mounting
02/07/2013US20130034936 Structure and method for power field effect transistor
02/07/2013US20130034935 Dicing die-bonding film
02/07/2013US20130034934 Wafer level package structure and method for manufacturing the same
02/07/2013US20130034925 Rfid based thermal bubble type accelerometer and method of manufacturing the same
02/07/2013US20130034918 Monitoring apparatus and method for in-situ measurement of wafer thicknesses for monitoring the thinning of semiconductor wafers and thinning apparatus comprising a wet etching apparatus and a monitoring apparatus
02/07/2013US20130034467 Method of making a microfluidic device
02/07/2013US20130034421 Method of processing a substrate in a lithography system
02/07/2013US20130033752 Diffraction-type 3d display element and method for fabricating the same
02/07/2013US20130033750 Stereoscopic image display device and method
02/07/2013US20130033705 Inspection device and inspection method
02/07/2013US20130033655 Thin film transistor substrate, method for producing same, and display device
02/07/2013US20130032955 Low-K Dielectric Layer and Porogen
02/07/2013US20130032954 Stackable integrated circuit package system
02/07/2013US20130032952 Semiconductor Device and Method of Forming POP With Stacked Semiconductor Die and Bumps Formed Directly on the Lower Die
02/07/2013US20130032950 Techniques for Interconnecting Stacked Dies Using Connection Sites
02/07/2013US20130032947 Semiconductor package and method of manufacturing the same
02/07/2013US20130032946 Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
02/07/2013US20130032945 Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication
02/07/2013US20130032944 Microelectronic package with stacked microelectronic elements and method for manufacture thereof
02/07/2013US20130032941 Routing layer for mitigating stress in a semiconductor die
02/07/2013US20130032937 Semiconductor device and associated method
02/07/2013US20130032936 Package for a mems sensor and manufacturing process thereof
02/07/2013US20130032935 Implementing enhanced thermal conductivity in stacked modules
02/07/2013US20130032934 Packaged microelectronic elements having blind vias for heat dissipation
02/07/2013US20130032930 Semiconductor device comprising through-electrode interconnect
02/07/2013US20130032929 Method of protecting deep trench sidewall from process damage
02/07/2013US20130032927 System for Self-Aligned Contacts
02/07/2013US20130032923 Integrated Inductor
02/07/2013US20130032922 Integrated high voltage divider
02/07/2013US20130032910 Magnetic memory device and method of manufacturing the same
02/07/2013US20130032908 Hybrid Film for Protecting MTJ Stacks of MRAM
02/07/2013US20130032905 Semiconductor package configured to electrically couple to a printed circuit board and method of providing same
02/07/2013US20130032904 Coated Capacitive Sensor
02/07/2013US20130032903 Integrated circuit with sensor and method of manufacturing such an integrated circuit
02/07/2013US20130032902 Integrated circuit with sensor and method of manufacturing such an integrated circuit
02/07/2013US20130032901 Full silicidation prevention via dual nickel deposition approach
02/07/2013US20130032900 Buffer layer and method of forming buffer layer
02/07/2013US20130032898 METAL-GATE/HIGH-k/GE MOSFET WITH LASER ANNEALING AND FABRICATION METHOD THEREOF
02/07/2013US20130032897 Mosfet gate electrode employing arsenic-doped silicon-germanium alloy layer
02/07/2013US20130032896 Semiconductor device and manufacturing method thereof
02/07/2013US20130032895 High-voltage transistor device and associated method for manufacturing
02/07/2013US20130032893 Semiconductor device comprising metal gate electrode structures and non-fets with different height by early adaptation of gate stack topography
02/07/2013US20130032892 Bipolar transistor in bipolar-cmos technology
02/07/2013US20130032891 Method of manufacturing an ic comprising a plurality of bipolar transistors and ic comprising a plurality of bipolar transistors
02/07/2013US20130032890 Self-adjusting latch-up resistance for cmos devices
02/07/2013US20130032888 Semiconductor device having insulating film with different stress levels in adjacent regions and manufacturing method thereof
02/07/2013US20130032887 Semiconductor device and manufacturing method thereof
02/07/2013US20130032886 Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET
02/07/2013US20130032885 Area efficient gridded polysilicon layouts
02/07/2013US20130032884 Integrated circuit device having defined gate spacing and method of designing and fabricating thereof
02/07/2013US20130032883 Fabrication of field-effect transistors with atomic layer doping