Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/1997
07/22/1997US5650956 Current amplification type mask-ROM
07/22/1997US5650919 Apparatus including a peak shaped dielectric dam
07/22/1997US5650915 Thermally enhanced molded cavity package having a parallel lid
07/22/1997US5650897 Wet etching the thick alumina layer and removing (in sequence) the metallic masking layers; studless; accuracy; stress relieving; reduced chipping; bonding strength; copper-free
07/22/1997US5650854 Method of checking defects in patterns formed on photo masks
07/22/1997US5650840 Focus detecting method and apparatus
07/22/1997US5650737 Protected switch
07/22/1997US5650733 Dynamic CMOS circuits with noise immunity
07/22/1997US5650732 Semiconductor device test system
07/22/1997US5650731 Photovoltaic oxide charge measurement probe technique
07/22/1997US5650667 Process of forming conductive bumps on the electrodes of semiconductor chips using lapping and the bumps thereby created
07/22/1997US5650664 Connector effecting an improved electrical connection and a semiconductor apparatus using such connector
07/22/1997US5650658 Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps
07/22/1997US5650657 Protection from short circuits between P and N wells
07/22/1997US5650656 Semiconductor memory device capable of storing plural-bit data in a single memory cell
07/22/1997US5650655 Integrated circuitry having electrical interconnects
07/22/1997US5650654 MOSFET device having controlled parasitic isolation threshold voltage
07/22/1997US5650651 Plasma damage reduction device for sub-half micron technology
07/22/1997US5650650 High speed semiconductor device with a metallic substrate
07/22/1997US5650649 Floating gate type field effect transistor having control gate applied with pulses for evacuating carriers from p-type semiconductor floating gate
07/22/1997US5650648 Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same
07/22/1997US5650647 Dynamic random access memory device and method of producing same
07/22/1997US5650646 Barriers for thermodynamic stability; semiconductor circuitry; capacitors; transistors; pixels for light detectors; electrooptic applications
07/22/1997US5650645 Field effect transistor having capacitor between source and drain electrodes
07/22/1997US5650642 Field effect semiconductor device
07/22/1997US5650639 Integrated circuit with diamond insulator
07/22/1997US5650638 Semiconductor device having a passivation layer
07/22/1997US5650631 Electron beam writing system
07/22/1997US5650595 Electronic module with multiple solder dams in soldermask window
07/22/1997US5650363 From melt blown thermoplastic microfibers, oleophilic
07/22/1997US5650362 Forming palladium layer on inside surface of porous ceramic tube, promotes decomposition of ammonia
07/22/1997US5650361 Low temperature photolytic deposition of aluminum nitride thin films
07/22/1997US5650360 Method for manufacturing semiconductor device with multilayer wiring structure, including improved step of forming insulating film which covers wiring layer
07/22/1997US5650358 Transformed microbe or plant cell, gene expression
07/22/1997US5650357 Process for manufacturing a lead frame capacitor and capacitively-coupled isolator circuit using same
07/22/1997US5650356 Automated clinical analyzers, sample holder manipulation, engaging/releasing mechanism
07/22/1997US5650355 Process of making and process of trimming a fuse in a top level metal and in a step
07/22/1997US5650354 Method for producing semiconductor device
07/22/1997US5650353 Method for production of SOI substrate
07/22/1997US5650351 Method to form a capacitor having multiple pillars for advanced DRAMS
07/22/1997US5650350 Semiconductor processing method of forming a static random access memory cell and static random access memory cell
07/22/1997US5650349 Forming a gate insulating layer on substrate having a first conductivity type and a gate electrode, source/drain regions are formed on substrate opposite side of electrode; doping n-type impurity in source/drain, serve as buried contact
07/22/1997US5650347 Method of manufacturing a lightly doped drain MOS transistor
07/22/1997US5650346 Method of forming MOSFET devices with buried bitline capacitors
07/22/1997US5650345 Method of making self-aligned stacked gate EEPROM with improved coupling ratio
07/22/1997US5650344 Method of making non-uniformly nitrided gate oxide
07/22/1997US5650343 Self-aligned implant energy modulation for shallow source drain extension formation
07/22/1997US5650342 Method of making a field effect transistor with a T shaped polysilicon gate electrode
07/22/1997US5650341 Process for fabricating CMOS Device
07/22/1997US5650340 Doping the substrate to form a pocket region with increased concentration of dopant located below trasnsitors drain and source region
07/22/1997US5650339 Method of manufacturing thin film transistor
07/22/1997US5650338 Method for forming thin film transistor
07/22/1997US5650337 Applying a controlled high electric field to a homogeneously, naturally-doped semiconductor to diffuse the naturally occurring impurities to create a homojunction; light-emitting diodes, phototransitors; radiation detectors
07/22/1997US5650336 Method of presuming life time of semiconductor device
07/22/1997US5650335 Ion implantation to correct for variations in carrier concentration determined by measuring electrical properties of formed field effect transistor (fet)
07/22/1997US5650262 High-resolution negative photoresist with wide process latitude
07/22/1997US5650199 Printing an electrode on a ceramic layer with conductive ink, printing a pattern, coating with wet ceramic slurry, drying and printing
07/22/1997US5650082 Profiled substrate heating
07/22/1997US5650075 Method for etching photolithographically produced quartz crystal blanks for singulation
07/22/1997US5650043 Etching method using NH4 F solution to make surface of silicon smooth in atomic order
07/22/1997US5650042 Substrate with insulating film, etching with gas for thinning
07/22/1997US5650041 Semiconductor device fabrication method
07/22/1997US5650040 Interfacial etch of silica to improve adherence of noble metals
07/22/1997US5650039 Chemical mechanical polishing apparatus with improved slurry distribution
07/22/1997US5650038 Method for dry etching
07/22/1997US5650032 Apparatus for producing an inductive plasma for plasma processes
07/22/1997US5650015 Dry method for cleaning semiconductor substrate
07/22/1997US5650013 Chemical vapor deposition, cleaning
07/22/1997US5649855 For polishing a semiconductor substrate wafer
07/17/1997WO1997025747A1 Epitaxial wafer of compound semiconductor
07/17/1997WO1997025745A1 Platinum-free ferroelectric memory cell with intermetallic barrier layer and method of making same
07/17/1997WO1997025744A1 Highly-integrated semiconductor memory and process for preparation of the memory
07/17/1997WO1997025743A1 Laser antifuse using gate capacitor
07/17/1997WO1997025740A1 Improved process for metals removal using beta-diketone or beta-ketoimine ligand forming compounds
07/17/1997WO1997025739A1 Electronic device manufacture with a laser beam
07/17/1997WO1997025738A2 A water vapor annealing process
07/17/1997WO1997025735A1 Electron beam pattern-writing column
07/17/1997WO1997025653A1 Three-dimensional etching process
07/17/1997DE4345408A1 Semiconductor wafer polishing appts.
07/17/1997DE19700517A1 Modified Czochralski single crystal growth process
07/17/1997DE19700516A1 Czochralski-type single crystal pulling apparatus
07/17/1997DE19700403A1 Czochralski-type single crystal pulling apparatus
07/17/1997CA2189417A1 Customizable integrated circuit device
07/16/1997EP0784347A2 Semiconductor device having capacitor
07/16/1997EP0784346A2 Charge transfer device and solid-state imaging apparatus using the same device
07/16/1997EP0784345A2 Switching circuit comprising field effect transistors
07/16/1997EP0784344A1 Semiconductor structure for resistive networks
07/16/1997EP0784341A1 Method of manufacture of material for semiconductor substrate, material for semiconductor substrate, and package for semiconductor
07/16/1997EP0784340A1 Method for contacting differently doped regions in a semicondutor device, and semiconductor device
07/16/1997EP0784339A2 Method of fabricating a semiconductor device
07/16/1997EP0784337A2 Method of removing a carbon-contaminated layer from a silicon substrate surface for subsequent selective silicon epitaxial growth thereon and apparatus for selective silicon epitaxial growth
07/16/1997EP0784336A2 Improvements in or relating to the fabrication and processing of semiconductor devices
07/16/1997EP0784206A2 Means for measuring the electric field
07/16/1997EP0784106A1 Epitaxial growth method
07/16/1997EP0783767A1 Bipolar transistor for use in linear amplifiers
07/16/1997EP0783727A1 Microstructures and methods for manufacturing microstructures
07/16/1997EP0783705A1 Method and apparatus for automated wafer level testing and reliability data analysis
07/16/1997EP0783532A1 Milled carbon fiber reinforced polymer composition
07/16/1997EP0700593A4 Releasing a workpiece from an electrostatic chuck
07/16/1997EP0693221B1 Forming a layer