Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2013
06/19/2013CN103165536A Pinch-off control of gate edge dislocation
06/19/2013CN103165535A Manufacturing method of complementary metal oxide semiconductor tube metal gate electrode
06/19/2013CN103165534A Manufacture method of metal grid of transistor of complementary metal-oxide-semiconductor (CMOS)
06/19/2013CN103165533A Process method for preventing defects of photoresist during wet etching
06/19/2013CN103165532A Method of manufacturing semiconductor element
06/19/2013CN103165531A Die structure and method of fabrication thereof
06/19/2013CN103165530A Thin film transistor (TFT) array substrate and manufacture method and display device thereof
06/19/2013CN103165529A Preparation method of array baseplate
06/19/2013CN103165528A Method of fabricating array substrate
06/19/2013CN103165527A Organic light-emitting display device and method of manufacturing the same
06/19/2013CN103165526A Producing method of array substrate, display panel and producing method thereof
06/19/2013CN103165525A Preparation method of thin film transistor (TFT) array substrate and preparation method of electro-static discharge (ESD) protective circuit on TFT array substrate
06/19/2013CN103165524A Insulated gate bipolar translator (IGBT) chip and manufacturing method of copper metallization structure on right side of IGBT chip
06/19/2013CN103165523A Manufacturing method of interconnection structure
06/19/2013CN103165522A Semiconductor structure and forming method of semiconductor structure
06/19/2013CN103165521A Method for repairing chip through laser
06/19/2013CN103165520A Manufacturing method of semiconductor device
06/19/2013CN103165519A Manufacturing method of semiconductor device
06/19/2013CN103165518A Manufacturing method of interconnected structure
06/19/2013CN103165517A Method for reducing interlayer dielectric layer dielectric constant
06/19/2013CN103165516A Manufacturing method of interconnected structure
06/19/2013CN103165515A Manufacture method of semiconductor device
06/19/2013CN103165514A Semiconductor structure and forming method thereof
06/19/2013CN103165513A Manufacturing method of interconnected structure
06/19/2013CN103165512A Extremely thin semiconductor-on-insulator material and preparation method thereof
06/19/2013CN103165511A Method for manufacturing germanium on insulator (GOI)
06/19/2013CN103165510A Shallow trench isolation structure and forming method thereof, semiconductor device structure and forming method thereof
06/19/2013CN103165509A Preparation method of silicon-on-quasi-insulator field-effect transistor
06/19/2013CN103165508A Semiconductor part manufacturing method
06/19/2013CN103165507A Method preventing electric leakage on shallow trough isolation edge
06/19/2013CN103165506A Wafer supporting structure
06/19/2013CN103165505A Methods of fabricating fan-out wafer level packages and packages formed by the methods
06/19/2013CN103165504A Track spin wafer chuck
06/19/2013CN103165503A Warping sheet tool and warping sheet tool using method and warping sheet connection device of warping sheet tool
06/19/2013CN103165502A Wafer tray and wafer box
06/19/2013CN103165501A Aligning method for unmarked substrate assembly
06/19/2013CN103165500A Multi-arm conveying mechanism of light chips
06/19/2013CN103165499A Front opening unified pod with latch structure
06/19/2013CN103165498A Manufacturing method of silicon slice load receptor
06/19/2013CN103165497A Oxidation reacting furnace and method utilizing the same to conduct oxidizing reaction
06/19/2013CN103165496A Substrate processing apparatus, substrate processing method and storage medium
06/19/2013CN103165495A Substrate holding and rotating device, substrate treatment apparatus including the device, and substrate treatment method
06/19/2013CN103165494A Cleaning device and method of polymer on reverse side of wafer
06/19/2013CN103165493A Detection device for system on package (SOP) type integrated circuit separation die
06/19/2013CN103165492A Optical microscopic image detection method for TSV (through silicon vias) of wafer
06/19/2013CN103165491A Device for monitoring temperature of electronic sucking disk
06/19/2013CN103165490A Method of detecting normality of wafer
06/19/2013CN103165489A Plasma immersion ion implantation (PIII) technological process control and on-line detection device of dose and evenness
06/19/2013CN103165488A Plasma immersion ion implantation (PIII) technological process control and on-line detection method of dose and evenness
06/19/2013CN103165487A Method for detecting grinding rate of pattern silicon wafers
06/19/2013CN103165486A Through silicon via detection structure and corresponding detection method
06/19/2013CN103165485A Monitoring method of millisecond annealing process stability
06/19/2013CN103165484A Stacked package and manufacturing method thereof
06/19/2013CN103165483A Method for reducing defects on aluminum gasket surface
06/19/2013CN103165482A Bump technology
06/19/2013CN103165481A Bump manufacture technology and structure thereof
06/19/2013CN103165480A Preparation method for flip chip salient point
06/19/2013CN103165479A Manufacture method of multi-chip and system-level packaging structure
06/19/2013CN103165478A Method of manufacturing semiconductor device
06/19/2013CN103165477A Method for forming vertical interconnect structure and semiconductor device
06/19/2013CN103165476A Integrated circuit package and packaging method
06/19/2013CN103165475A Manufacture method of semiconductor package component
06/19/2013CN103165474A Method for producing semiconductor device
06/19/2013CN103165473A Manufacturing method of bump and semiconductor device manufacturing method
06/19/2013CN103165472A Fiber channel (FC)-ball grid array (BGA) packaging bump distributed heat dissipation novel method
06/19/2013CN103165471A Thin film transistor and manufacture method and display device thereof
06/19/2013CN103165470A Preparing method of side grid graphene transistor based on copper (Cu) membrane annealing and chlorine (Cl2) reaction
06/19/2013CN103165469A Preparing method of side grid graphene transistor on silicon (Si) substrate based on copper (Cu) membrane annealing
06/19/2013CN103165468A Preparing method of side grid graphene transistor through reaction of silicon carbide (SiC) and chlorine gas (Cl2) based on copper (Cu) membrane annealing
06/19/2013CN103165467A Manufacturing method of side grid graphene transistor on silicon carbide (SiC) substrate based on copper (Cu) membrane annealing
06/19/2013CN103165466A Semiconductor device including polysilicon resistor and metal gate resistor and methods of fabricating thereof
06/19/2013CN103165465A P-channel metal oxide semiconductor (PMOS) manufacturing method utilizing e-SiGe
06/19/2013CN103165464A P-channel metal oxide semiconductor (PMOS) manufacturing method using e-SiGe
06/19/2013CN103165463A Manufacturing method of semiconductor device
06/19/2013CN103165462A Method for manufacturing suspended nanowire channel-type metal-oxide -semiconductor field effect transistor (MOSFET)
06/19/2013CN103165461A Method for manufacturing semiconductor device
06/19/2013CN103165460A Manufacturing methods for LDNMOS and LDPMOS
06/19/2013CN103165459A Fin field effect transistor and manufacturing method of the same
06/19/2013CN103165458A Manufacturing method of metal-oxide-semiconductor field effect transistor (MOSFET)
06/19/2013CN103165457A Manufacturing method of semiconductor device
06/19/2013CN103165456A Method of enhancing metal-oxide-semiconductor field effect transistor (MOSFET) performance through corner stress of STI
06/19/2013CN103165455A Method for manufacturing fin-shaped field effect transistor
06/19/2013CN103165454A Semiconductor device and manufacturing method of the same
06/19/2013CN103165453A High-dielectric metal gate metal oxide semiconductor (MOS) and manufacturing method thereof
06/19/2013CN103165452A Transistor of lateral diffused metal-oxide-semiconductor (LDMOS) and manufacture method thereof
06/19/2013CN103165451A Structure of semiconductor device and manufacture method
06/19/2013CN103165450A Manufacturing method of terminal ring
06/19/2013CN103165449A Manufacturing method of semiconductor device
06/19/2013CN103165448A Forming method of transistor of P-channel metal oxide semiconductor (PMOS)
06/19/2013CN103165447A Fin type field effect transistor and manufacture method thereof
06/19/2013CN103165446A HEMT (high electron mobility transistor) device available for silicon-based integration and method for preparing HEMT device
06/19/2013CN103165445A In situ grown gate dielectric and field plate dielectric
06/19/2013CN103165444A High-quality gan high-voltage hfets on silicon
06/19/2013CN103165443A Insulated gate transistor device and manufacturing technology method thereof
06/19/2013CN103165442A Back side graphical method
06/19/2013CN103165441A Manufacturing method of high-k grid electrode dielectric medium\metal stack-up grid electrode
06/19/2013CN103165440A Manufacturing method of high-dielectric-constant metal grid electrode semiconductor device
06/19/2013CN103165439A Blocking layer in contact hole and manufacturing method for blocking layer
06/19/2013CN103165438A Method of manufacturing semiconductor device, method of processing substrate, substrate processing apparatus
06/19/2013CN103165437A Gate-oxide etching method and multi-grid-electrode manufacturing method