Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2013
06/20/2013US20130157389 Multiple-Patterning Overlay Decoupling Method
06/20/2013US20130157388 Etch rate detection for anti-reflective coating layer and absorber layer etching
06/20/2013US20130157387 Multi-zone EPD Detectors
06/20/2013US20130157386 Semiconductor apparatus and repairing method thereof
06/20/2013US20130157382 Profile method in magnetic write head fabrication
06/20/2013US20130156947 Track Spin Wafer Chuck
06/20/2013US20130156530 Method and apparatus for reducing contamination of substrate
06/20/2013US20130156364 Electronic/photonic integrated circuit architecture and method of manufacture thereof
06/20/2013US20130155796 Fabrication and testing method for nonvolatile memory devices
06/20/2013US20130155771 3d non-volatile memory device, memory system including the same, and method of manufacturing the same
06/20/2013US20130155568 Extended and independent rf powered cathode substrate for extreme edge tunability
06/20/2013US20130155481 Display device and method for manufacturing the display device
06/20/2013US20130155364 Method of reducing parasitic capacitance of liquid crystal display device and liquid crystal display device
06/20/2013US20130155342 Array substrate, liquid crystal display panel and broken-line repairing method thereof
06/20/2013US20130154748 Apparatus and Method for Thermal Interfacing
06/20/2013US20130154687 Semiconductor Device Having Features to Prevent Reverse Engineering
06/20/2013US20130154175 Process kit components for use with an extended and independent rf powered cathode substrate for extreme edge tunability
06/20/2013US20130154124 Method for packaging semiconductors at a wafer level
06/20/2013US20130154123 Semiconductor Device and Fabrication Method
06/20/2013US20130154121 Integrated circuit packaging system with film assistance mold and method of manufacture thereof
06/20/2013US20130154120 Integrated circuit packaging system with package-on-package and method of manufacture thereof
06/20/2013US20130154119 Integrated circuit packaging system with terminals and method of manufacture thereof
06/20/2013US20130154118 Integrated circuit packaging system with contacts and method of manufacture thereof
06/20/2013US20130154116 Integrated circuit packaging system with perimeter antiwarpage structure and method of manufacture thereof
06/20/2013US20130154115 Integrated circuit packaging system with leads and method of manufacture thereof
06/20/2013US20130154112 Method for Forming Isolation Trenches in Micro-Bump Interconnect Structures and Devices Obtained Thereof
06/20/2013US20130154111 Semiconductor device including through electrode and method of manufacturing the same and stacked package including semiconductor device and method of manufacturing the same
06/20/2013US20130154110 Direct write interconnections and method of manufacturing thereof
06/20/2013US20130154109 Method of lowering capacitances of conductive apertures and an interposer capable of being reverse biased to achieve reduced capacitance
06/20/2013US20130154108 Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP
06/20/2013US20130154107 Integrated circuit packaging system with coupling features and method of manufacture thereof
06/20/2013US20130154106 Stacked Packaging Using Reconstituted Wafers
06/20/2013US20130154105 Integrated circuit packaging system with routable trace and method of manufacture thereof
06/20/2013US20130154101 Semiconductor device and method for manufacturing the same
06/20/2013US20130154100 Method of patterning a semiconductor device having improved spacing and shape control and a semiconductor device
06/20/2013US20130154096 Semiconductor device and manufacturing method thereof
06/20/2013US20130154092 Integrated circuit packaging system with conductive pillars and method of manufacture thereof
06/20/2013US20130154091 Semiconductor device packaging using encapsulated conductive balls for package-on-package back side coupling
06/20/2013US20130154090 Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties
06/20/2013US20130154089 Bump including diffusion barrier bi-layer and manufacturing method thereof
06/20/2013US20130154088 Integrated Circuits with Components on Both Sides of a Selected Substrate and Methods of Fabrication
06/20/2013US20130154087 Method for forming interconnection pattern and semiconductor device
06/20/2013US20130154086 Exposing Connectors in Packages Through Selective Treatment
06/20/2013US20130154085 Integrated circuit packaging system with heat conduction and method of manufacture thereof
06/20/2013US20130154082 Semiconductor device, semiconductor device manufacturing method, and electronic device
06/20/2013US20130154080 Integrated circuit packaging system with leads and method of manufacture thereof
06/20/2013US20130154079 Integrated circuit packaging system with substrate mold gate and method of manufacture thereof
06/20/2013US20130154078 Integrated circuit packaging system with heat slug and method of manufacture thereof
06/20/2013US20130154077 Chip package and method for forming the same
06/20/2013US20130154074 Semiconductor stack packages and methods of fabricating the same
06/20/2013US20130154073 Method of forming a semiconductor device and leadframe therefor
06/20/2013US20130154072 Integrated circuit packaging system with pad and method of manufacture thereof
06/20/2013US20130154068 Packaged leadless semiconductor device
06/20/2013US20130154065 Process for treating a substrate using a luminous flux of determined wafelength, and corresponding substrate
06/20/2013US20130154064 Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device
06/20/2013US20130154063 Driving substrate, display device, planarizing method, and method of manufacturing driving substrate
06/20/2013US20130154062 Die Structure and Method of Fabrication Thereof
06/20/2013US20130154061 Anodizing apparatus, an anodizing system having the same, and a semiconductor wafer
06/20/2013US20130154060 Wafer and method of processing wafer
06/20/2013US20130154059 Semiconductor device manufacturing method and semiconductor device
06/20/2013US20130154055 Capacitor and register of semiconductor device, memory system including the semiconductor device, and method of manufacturing the semiconductor device
06/20/2013US20130154053 Inductors with through vias
06/20/2013US20130154051 Method for forming a deep trench in a microelectronic component substrate
06/20/2013US20130154050 Integrated Circuit and IC Manufacturing Method
06/20/2013US20130154049 Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology
06/20/2013US20130154048 Guard Ring for Through Vias
06/20/2013US20130154034 Method and system for setting a pinned layer in a magnetic tunneling junction
06/20/2013US20130154027 Memory Cell
06/20/2013US20130154026 Contact structures for semiconductor transistors
06/20/2013US20130154022 CMOS Devices with Metal Gates and Methods for Forming the Same
06/20/2013US20130154021 Enhanced gate replacement process for high-k metal gate technology
06/20/2013US20130154020 System, method and apparatus for seedless electroplated structure on a semiconductor substrate
06/20/2013US20130154019 Low threshold voltage cmos device
06/20/2013US20130154014 Semiconductor Device and Method for Fabricating the Same
06/20/2013US20130154013 Semiconductor device and method of manufacturing the same
06/20/2013US20130154012 Manufacturing method for semiconductor device having metal gate
06/20/2013US20130154011 Methods and Apparatus for Reduced Gate Resistance FinFET
06/20/2013US20130154007 Rare-earth oxide isolated semiconductor fin
06/20/2013US20130154006 Finfet with vertical silicide structure
06/20/2013US20130154004 Semiconductor device with biased feature
06/20/2013US20130154003 Asymmetric anti-halo field effect transistor
06/20/2013US20130154002 FinFETs with Multiple Threshold Voltages
06/20/2013US20130154001 Embedded stressors for multigate transistor devices
06/20/2013US20130153997 Hybrid cmos nanowire mesh device and bulk cmos device
06/20/2013US20130153996 Hybrid cmos nanowire mesh device and pdsoi device
06/20/2013US20130153995 Semiconductor device and method for manufacturing the same
06/20/2013US20130153994 Trench type power transistor device with super junction and manufacturing method thereof
06/20/2013US20130153993 Hybrid cmos nanowire mesh device and finfet device
06/20/2013US20130153992 Electronic device including a tapered trench and a conductive structure therein and a process of forming the same
06/20/2013US20130153991 Electronic device comprising conductive structures and an insulating layer between the conductive structures and within a trench and a process of forming the same
06/20/2013US20130153988 Electronic device including a trench with a facet and a conductive structure therein and a process of forming the same
06/20/2013US20130153987 Electronic device comprising a conductive structure and an insulating layer within a trench and a process of forming the same
06/20/2013US20130153983 3-d nonvolatile memory device, memory system including the 3-d nonvolatile memory device, and method of manufacturing the 3-d nonvolatile memory device
06/20/2013US20130153981 Nonvolatile memory devices and methods of manufacturing the same
06/20/2013US20130153980 Nonvolatile semiconductor memory device and method of manufacturing the same
06/20/2013US20130153979 Three-dimensional non-volatile memory device, memory system and method of manufacturing the same
06/20/2013US20130153978 3d non-volatile memory device and method of manufacturing the same
06/20/2013US20130153971 V-groove source/drain mosfet and process for fabricating same
06/20/2013US20130153970 Transistor structure, method for manufacturing a transistor structure, force-measuring system
06/20/2013US20130153968 Semiconductor Device