Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2013
06/27/2013US20130161801 Module Including a Discrete Device Mounted on a DCB Substrate
06/27/2013US20130161798 Graded density layer for formation of interconnect structures
06/27/2013US20130161797 Single crystal substrate, manufacturing method for single crystal substrate, manufacturing method for single crystal substrate with multilayer film, and element manufacturing method
06/27/2013US20130161796 Through silicon via and method of forming the same
06/27/2013US20130161795 Manufacturing method of semiconductor device, processing method of semiconductor wafer, semiconductor wafer
06/27/2013US20130161794 Internally reformed substrate for epitaxial growth, internally reformed substrate with multilayer film, semiconductor device, bulk semiconductor substrate, and manufacturing methods therefor
06/27/2013US20130161793 Silicon Single Crystal Substrate and Method Of Manufacturing The Same
06/27/2013US20130161786 Capacitor array and method of fabricating the same
06/27/2013US20130161783 Semiconductor device including isolation layer and method for fabricating the same
06/27/2013US20130161782 Heterogeneous Chip Integration with Low Loss Interconnection through Adaptive Patterning
06/27/2013US20130161780 Method of fabricating a gan p-i-n diode using implantation
06/27/2013US20130161767 Semiconductor devices having polysilicon gate patterns and methods of fabricating the same
06/27/2013US20130161763 Source-drain extension formation in replacement metal gate transistor device
06/27/2013US20130161762 Gate structure for semiconductor device
06/27/2013US20130161758 Buried Power Grid Designs and the Methods for Forming Buried Power Grids in CMOS Technologies for Improved Radiation Hardness
06/27/2013US20130161757 CMOS Device for Reducing Charge Sharing Effect and Fabrication Method Thereof
06/27/2013US20130161756 Nanowire transistor devices and forming techniques
06/27/2013US20130161755 Thin film transistor and fabricating method
06/27/2013US20130161754 Semiconductor device and fabricating method thereof
06/27/2013US20130161744 Finfet with merged fins and vertical silicide
06/27/2013US20130161742 Semiconductor device and fabricating method thereof
06/27/2013US20130161741 Semiconductor device and method of manufacturing the same
06/27/2013US20130161740 Lateral High-Voltage Transistor with Buried Resurf Layer and Associated Method for Manufacturing the Same
06/27/2013US20130161739 Dummy gate for a high voltage transistor device
06/27/2013US20130161737 Semiconductor device and method of manufacturing the same
06/27/2013US20130161736 Trench metal oxide semiconductor transistor device and manufacturing method thereof
06/27/2013US20130161735 Transistor structure and method for preparing the same
06/27/2013US20130161731 Semiconductor device and method of manufacturing the same
06/27/2013US20130161730 Memory array structure and method for forming the same
06/27/2013US20130161729 Methods of Forming Isolation Structures on FinFET Semiconductor Devices
06/27/2013US20130161726 Non-volatile memory device and method for fabricating the same
06/27/2013US20130161725 Semiconductor memory device and method of manufacturing the same
06/27/2013US20130161724 3-dimensional non-volatile memory device, memory system including the same, and method of manufacturing the device
06/27/2013US20130161719 Integrated Nanostructure-Based Non-Volatile Memory Fabrication
06/27/2013US20130161717 Non-volatile memory device and method for fabricating the same
06/27/2013US20130161716 Semiconductor device with selectively located air gaps and method of fabrication
06/27/2013US20130161715 Vertical transistor structure and method of manufacturing same
06/27/2013US20130161710 Semiconductor device having buried bit line and method for fabricating the same
06/27/2013US20130161709 Semiconductor device and method of manufacturing the same
06/27/2013US20130161708 Semiconductor structure and method for manufacturing the same
06/27/2013US20130161707 Resistive Memory and Methods for Forming the Same
06/27/2013US20130161705 Method and system for a gan vertical jfet with self-aligned source and gate
06/27/2013US20130161703 Sensor element array and method of fabricating the same
06/27/2013US20130161700 Method of manufacturing sidewall spacers on a memory device
06/27/2013US20130161699 Semiconductor structures having nucleation layer to prevent interfacial charge for column iii-v materials on column iv or column iv-iv materials
06/27/2013US20130161698 E-mode hfet device
06/27/2013US20130161696 Tunnel field-effect transistor and methods for manufacturing thereof
06/27/2013US20130161694 Thin hetereostructure channel device
06/27/2013US20130161693 Thin hetereostructure channel device
06/27/2013US20130161689 Insulated gate bipolar transistor structure having low substrate leakage
06/27/2013US20130161670 Light emitting diode packages and methods of making
06/27/2013US20130161663 Electro-optic displays, and components for use therein
06/27/2013US20130161648 Diamond Semiconductor System and Method
06/27/2013US20130161638 High electron mobility transistor structure with improved breakdown voltage performance
06/27/2013US20130161637 Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods
06/27/2013US20130161636 Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods
06/27/2013US20130161635 Method and system for a gan self-aligned vertical mesfet
06/27/2013US20130161634 Method and system for fabricating edge termination structures in gan materials
06/27/2013US20130161633 Method and system for junction termination in gan materials using conductivity modulation
06/27/2013US20130161629 Zero shrinkage smooth interface oxy-nitride and oxy-amorphous-silicon stacks for 3d memory vertical gate application
06/27/2013US20130161625 Array substrate and manufacturing method thereof
06/27/2013US20130161623 Semiconductor device
06/27/2013US20130161620 Composition for an oxide thin film, a preparation method of the composition, a method for forming an oxide thin film using the composition, an electronic device including the oxide thin film, and a semiconductor device including the oxide thin film
06/27/2013US20130161618 Silicon-on-insulator (soi) structure configured for reduced harmonics and method of forming the structure
06/27/2013US20130161617 Method for measuring impurity concentration profile, wafer used for same, and method for manufacturing semiconductor device using same
06/27/2013US20130161615 Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations
06/27/2013US20130161611 Semiconductor device and method for manufacturing the same
06/27/2013US20130161604 Pixel structure and manufacturing method thereof
06/27/2013US20130161587 Graphene devices and methods of manufacturing the same
06/27/2013US20130161582 Conductive bridging memory device and method for manufacturing same
06/27/2013US20130161573 Lead-free conductive paste composition and semiconductor devices made therewith
06/27/2013US20130161572 Conductive paste composition with synthetic clay additive and its use in the manufacture of semiconductor devices
06/27/2013US20130161534 Method of manufacturing white light emitting device (led) and apparatus measuring phosphor film
06/27/2013US20130161313 Heat-treatment furnace
06/27/2013US20130161312 Laser-irradiated thin films having variable thickness
06/27/2013US20130160952 Apparatuses for bonding semiconductor chips
06/27/2013US20130160949 Plasma processing apparatus
06/27/2013US20130160946 Purging of porogen from uv cure chamber
06/27/2013US20130160831 Reactive Sputtering of ZnS(O,H) and InS(O,H) for Use as a Buffer Layer
06/27/2013US20130160830 Thick-film conductive paste composition
06/27/2013US20130160795 Plasma Etcher Design with Effective No-Damage In-Situ Ash
06/27/2013US20130160794 Methods and apparatus for cleaning substrate surfaces with atomic hydrogen
06/27/2013US20130160705 Reduction of edge chipping during wafer handling
06/27/2013US20130160574 Penetrable cap
06/27/2013US20130160261 Apparatus for manufacturing semiconductor wafer
06/27/2013US20130160260 Apparatus for treating surfaces of wafer-shaped articles
06/27/2013DE19647324B4 Halbleiterbauelement Semiconductor device
06/27/2013DE112011103232T5 Oberflächenbehandlungszusammensetzung und Oberflächenbehandlungsverfahren unter Verwendung derselben The surface treatment composition and surface treatment method using the same
06/27/2013DE112011103109T5 Zeichenverfahren und Zeichenvorrichtung The drawing method and drawing device
06/27/2013DE112011102676T5 Substratwärmebehandlungsgerät, Temperatursteuerungsverfahren für Substratwärmebehandlungsgerät, Herstellungsverfahren für Halbleitervorrichtung, Temperatursteuerprogramm für Substratwärmebehandlungsgerät und Aufzeichnungsträger Substrate heat-treating device, temperature control method for substrate heat treatment apparatus, manufacturing method of semiconductor device, temperature control program for the substrate heat treatment apparatus and record carrier
06/27/2013DE112011102528T5 Siliziumkarbid-Substrat, Halbleitervorrichtung und Verfahren zum Herstellen derselben Silicon carbide substrate, semiconductor device, and method for manufacturing the same
06/27/2013DE112011102207T5 Zuführvorrichtung für reaktive Spezies und Oberflächenbehandlungseinrichtung Feeder reactive species and surface treatment device
06/27/2013DE112010005118T5 Hardware-synthese unter verwendung von wärmebewusster einplanung und einbindung Hardware synthesis by use of heat-conscious scheduling and incorporating your
06/27/2013DE112010004021T5 Transistoren mit Halbleiterverbindungsschichten und Halbleiterkanalschichten unterschiedlichen Halbleitermaterials Transistors with compound semiconductor layers and semiconductor channel layers of different semiconductor material
06/27/2013DE112009001633B4 Feinstruktur und Prägestempel Fine structure and dies
06/27/2013DE112009000670B4 Verfahren zum Herstellen einer Metall-Gate-Struktur A method of manufacturing a metal gate structure
06/27/2013DE10205870B4 Moduleinheit mit SiC-Halbleiterbauelement mit Schottky-Kontakten Module unit with SiC semiconductor device with Schottky contacts
06/27/2013DE102012224047A1 Verbundhalbleiterbauelement mt vergrabener Feldplatte und Verfahren zum Herstellen eines Halbleiterbauelements Composite semiconductor device mt buried field plate and method for manufacturing a semiconductor device
06/27/2013DE102012223655A1 Bildung von Source-Drain-Erweiterungen in Metall-Ersatz-Gate-Transistoreinheit Formation of source-drain extensions in metal replacement gate transistor unit
06/27/2013DE102012222786A1 Verfahren zur fertigung einer halbleitervorrichtung A method of manufacturing a semiconductor device
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