Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2013
06/27/2013WO2013091142A1 Lead frame pad containing microchannels for packaging high-power electronic component, packaging structure and process
06/27/2013WO2013040557A3 Rna engineered t cells for the treatment of cancer
06/27/2013WO2013040063A3 Determining design coordinates for wafer defects
06/27/2013WO2013039866A4 Activated silicon precursors for low temperature deposition
06/27/2013WO2013033443A3 Beol interconnect with carbon nanotubes
06/27/2013WO2013025024A4 Ingot growing apparatus and method of manufacturing ingot
06/27/2013WO2013023029A8 Aion coated substrate with optional yttria overlayer
06/27/2013WO2013003420A4 A semiconductor substrate and method of manufacturing
06/27/2013WO2012177313A3 Semiconductor structure having an integrated quadruple-wall capacitor for embedded dynamic random access memory (edram) and method to form the same
06/27/2013WO2012050812A8 Semiconductor die having fine pitch electrical interconnects
06/27/2013US20130166248 Monitor Test Key of Epi Profile
06/27/2013US20130166057 Methods for forming small-scale capacitor structures
06/27/2013US20130164948 Methods for improving wafer temperature uniformity
06/27/2013US20130164947 Titanium-containing precursors for vapor deposition
06/27/2013US20130164946 Method of forming silicon oxycarbonitride film
06/27/2013US20130164945 Film deposition method
06/27/2013US20130164944 Methods Of Forming Openings And Methods Of Patterning A Material
06/27/2013US20130164943 Substrate Processing Apparatus and Method of Manufacturing Semiconductor Device
06/27/2013US20130164942 Film deposition method
06/27/2013US20130164941 Plasma reactor with adjustable plasma electrodes and associated methods
06/27/2013US20130164940 Highly selective spacer etch process with reduced sidewall spacer slimming
06/27/2013US20130164939 Method, apparatus for holding and treatment of a substrate
06/27/2013US20130164938 Selective Bias Compensation for Patterning Steps in CMOS Processes
06/27/2013US20130164937 Chemical mechanical planarization site isolation reactor
06/27/2013US20130164935 Low resistance through-wafer via
06/27/2013US20130164934 Manufacturing method of a semiconductor device and method for creating a layout thereof
06/27/2013US20130164933 Hydrogen barrier for ferroelectric capacitors
06/27/2013US20130164932 Methods of forming wirings in electronic devices
06/27/2013US20130164931 Metal Structure for Memory Device
06/27/2013US20130164930 Gate height loss improvement for a transistor
06/27/2013US20130164929 Non-volatile semiconductor memory device and method of manufacturing the same
06/27/2013US20130164928 Semiconductor Device and Method for Forming the Same
06/27/2013US20130164926 Method of manufacturing semiconductor device
06/27/2013US20130164925 Method of manufacturing semiconductor memory device
06/27/2013US20130164924 Structure and Method for Fabricating Fin Devices
06/27/2013US20130164922 Methods of manufacturing a semiconductor device
06/27/2013US20130164921 High-density nonvolatile memory and methods of making the same
06/27/2013US20130164920 Method for manufacturing semiconductor device
06/27/2013US20130164919 Methods of fabricating semiconductor devices and methods of fabricating gate insulating layers
06/27/2013US20130164918 Absorbers For High-Efficiency Thin-Film PV
06/27/2013US20130164917 Absorbers For High-Efficiency Thin-Film PV
06/27/2013US20130164916 Absorbers for high efficiency thin-film pv
06/27/2013US20130164915 Method for fabricating power semiconductor device with super junction structure
06/27/2013US20130164914 Laser processing method for wafer
06/27/2013US20130164913 Semiconductor device manufacturing method
06/27/2013US20130164912 Reduction of edge chipping during wafer handling
06/27/2013US20130164911 Plasma processing method
06/27/2013US20130164910 Devices with gate-to-gate isolation structures and methods of manufacture
06/27/2013US20130164909 Method of manufacturing semiconductor device
06/27/2013US20130164908 Manufacturing method of thin film transistor array substrate
06/27/2013US20130164907 Methods of forming a thin film and methods of fabricating a semiconductor device including using the same
06/27/2013US20130164906 Full wafer processing by multiple passes through a combinatorial reactor
06/27/2013US20130164903 Method for fabricating capacitor of semiconductor device
06/27/2013US20130164902 Methods Of Forming Capacitors
06/27/2013US20130164901 Method of Making Capacitor With a Sealing Liner and Semiconductor Device Comprising Same
06/27/2013US20130164899 Semiconductor device and method for manufacturing the same
06/27/2013US20130164894 Method of fabricating a three-dimentional semiconductor memory device
06/27/2013US20130164893 Fabrication of floating guard rings using selective regrowth
06/27/2013US20130164890 Method for fabricating finfet with merged fins and vertical silicide
06/27/2013US20130164889 Semiconductor device and method of manufacturing the same
06/27/2013US20130164885 Absorbers For High-Efficiency Thin-Film PV
06/27/2013US20130164875 Buffer layers for organic electroluminescent devices and methods of manufacture and use
06/27/2013US20130164874 Methods of forming dilute nitride materials for use in photoactive devices and related structures
06/27/2013US20130164688 Support, Lithographic Apparatus and Device Manufacturing Method
06/27/2013US20130164685 Method and apparatus for drying a wafer
06/27/2013US20130164677 Spin-On Anti-Reflective Coatings for Photolithography
06/27/2013US20130164113 Robotic device for substrate transfer applications
06/27/2013US20130164101 Robot arm structure and robot
06/27/2013US20130163919 Optoelectronic chips including coupler region and methods of manufacturing the same
06/27/2013US20130163916 Optical waveguide platform with hybrid-integrated optical transmission device and optical active device and method of manufacturing the same
06/27/2013US20130163852 Rotational multi-layer overlay marks, apparatus, and methods
06/27/2013US20130163631 Conformal metallization process for the fabrication of semiconductor laser devices
06/27/2013US20130163628 Process for forming microstructure of nitride semiconductor, surface emitting laser using two-dimensional photonic crystal and production process thereof
06/27/2013US20130163306 One-Time Programmable Memory Cell, Memory and Manufacturing Method Thereof
06/27/2013US20130163139 Variable breakdown transient voltage suppressor
06/27/2013US20130162925 Thin-film Transistor Substrate and Manufacturing Method Thereof and Liquid Crystal Display Device
06/27/2013US20130162727 Substrate, liquid ejection head having such substrate and method of manufacturing such substrate
06/27/2013US20130162724 Protecting a fluid ejection device resistor
06/27/2013US20130162282 Semiconductor device having potential monitoring terminal to monitor potential of power-supply line
06/27/2013US20130162173 Light source circuit boards
06/27/2013US20130161841 Alignment mark and method of manufacturing the same
06/27/2013US20130161840 Stripper solutions effective for back-end-of-line operations
06/27/2013US20130161839 Semiconductor device and method of manufacturing the same
06/27/2013US20130161837 Semiconductor package, packaging substrate and fabrication method thereof
06/27/2013US20130161834 Heterogeneous integration process incorporating layer transfer in epitaxy level packaging
06/27/2013US20130161833 Semiconductor Device and Method of Forming Extended Semiconductor Device with Fan-Out Interconnect Structure to Reduce Complexity of Substrate
06/27/2013US20130161832 Semiconductor device with buried bit line and method for fabricating the same
06/27/2013US20130161828 Tsv via provided with a stress release structure and its fabrication method
06/27/2013US20130161825 Through substrate via structure and method for fabricating the same
06/27/2013US20130161824 Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief
06/27/2013US20130161821 Nonvolatile memory device and method of manufacturing the same
06/27/2013US20130161820 Method for bonding two silicon substrates, and a correspondeing system of two silicon substrates
06/27/2013US20130161818 3-d nonvolatile memory device and method of manufacturing the same
06/27/2013US20130161817 Techniques for wafer-level processing of qfn packages
06/27/2013US20130161813 Semiconductor device, semiconductor package, and method for manufacturing semiconductor device
06/27/2013US20130161811 3d ic configuration with contactless communication
06/27/2013US20130161809 Substrate structure, semiconductor package device, and manufacturing method of substrate structure
06/27/2013US20130161806 Window clamp top plate for integrated circuit packaging
06/27/2013US20130161804 Integrated circuit (ic) leadframe design
06/27/2013US20130161802 Semiconductor package having electrical connecting structures and fabrication method thereof