| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 07/11/2013 | US20130178072 In-situ chamber cleaning for an rtp chamber |
| 07/11/2013 | US20130178071 Thermal oxide film formation method for silicon single crystal wafer |
| 07/11/2013 | US20130178070 Atomic layer deposition apparatus |
| 07/11/2013 | US20130178069 Silicon etching fluid and method for producing transistor using same |
| 07/11/2013 | US20130178068 Dual damascene process and apparatus |
| 07/11/2013 | US20130178067 Method of manufacturing a semiconductor device |
| 07/11/2013 | US20130178066 Method and apparatus for manufacturing three-dimensional-structure memory device |
| 07/11/2013 | US20130178065 Method and Composition for Chemical Mechanical Planarization of a Metal |
| 07/11/2013 | US20130178064 Polishing slurry and chemical mechanical planarization method using the same |
| 07/11/2013 | US20130178063 Method of manufacturing semiconductor device having silicon through via |
| 07/11/2013 | US20130178062 3d ic method and device |
| 07/11/2013 | US20130178061 Method of manufacturing porous film and method of manufacturing semiconductor device |
| 07/11/2013 | US20130178060 Method for Manufacturing a Barrier Layer on a Substrate and a Multi-Layer Stack |
| 07/11/2013 | US20130178059 Manufacturing method and manufacturing apparatus of device |
| 07/11/2013 | US20130178058 INTERCONNECT STRUCTURE EMPLOYING A Mn-GROUP VIIIB ALLOY LINER |
| 07/11/2013 | US20130178057 Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique |
| 07/11/2013 | US20130178056 Field effect transistor having an asymmetric gate electrode |
| 07/11/2013 | US20130178055 Methods of Forming a Replacement Gate Electrode With a Reentrant Profile |
| 07/11/2013 | US20130178054 Methods of making logic transistors and non-volatile memory cells |
| 07/11/2013 | US20130178052 Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts |
| 07/11/2013 | US20130178051 Method of Impurity Introduction and Controlled Surface Removal |
| 07/11/2013 | US20130178050 Method for manufacturing gallium nitride wafer |
| 07/11/2013 | US20130178049 Method of manufacturing substrate |
| 07/11/2013 | US20130178048 Method of fabricating semiconductor device having buried wiring and related device |
| 07/11/2013 | US20130178047 Highly Luminescent II-V Semiconductor Nanocrystals |
| 07/11/2013 | US20130178046 Method of manufacturing a semiconductor apparatus |
| 07/11/2013 | US20130178045 Method of Forming Transistor with Increased Gate Width |
| 07/11/2013 | US20130178044 Semiconductor devices comprising a plurality of gate structures |
| 07/11/2013 | US20130178043 Integrated Circuit Including DRAM and SRAM/Logic |
| 07/11/2013 | US20130178040 Reprocessing method of a semiconductor device |
| 07/11/2013 | US20130178039 Integrated circuit resistor fabrication with dummy gate removal |
| 07/11/2013 | US20130178034 Methods of Making Transistor Devices with Elevated Source/Drain Regions to Accommodate Consumption During Metal Silicide Formation Process |
| 07/11/2013 | US20130178031 Integration of non-volatile charge trap memory devices and logic cmos devices |
| 07/11/2013 | US20130178030 Method of ono integration into logic cmos flow |
| 07/11/2013 | US20130178029 Method of forming a semiconductor device |
| 07/11/2013 | US20130178025 Methods Of Fabricating A Memory Device |
| 07/11/2013 | US20130178024 In Situ Doping and Diffusionless Annealing of Embedded Stressor Regions in PMOS and NMOS Devices |
| 07/11/2013 | US20130178022 Method for fabricating transistor with recessed channel and raised source/drain |
| 07/11/2013 | US20130178021 Integrated circuit with a thin body field effect transistor and capacitor |
| 07/11/2013 | US20130178020 Finfet with fully silicided gate |
| 07/11/2013 | US20130178019 Nanowire Field Effect Transistors |
| 07/11/2013 | US20130178018 Semiconductor module, molding apparatus, and molding method |
| 07/11/2013 | US20130178017 Method for manufacturing semiconductor chips from a semiconductor wafer |
| 07/11/2013 | US20130178014 Method for manufacturing a gate-control diode semiconductor memory device |
| 07/11/2013 | US20130178013 Method for manufacturing a gate-control diode semiconductor device |
| 07/11/2013 | US20130178012 Method for manufacturing a gate-control diode semiconductor device |
| 07/11/2013 | US20130178006 Wafer dicing method and method of manufacturing light emitting device chips employing the same |
| 07/11/2013 | US20130177999 Methods for fabricating integrated circuits including in-line diagnostics performed on low-k dielectric layers |
| 07/11/2013 | US20130177998 Method of manufacturing light emitting device and phosphor-containing fluid resin dispensing apparatus |
| 07/11/2013 | US20130177997 Semiconductor device and method of manufacturing the semiconductor device |
| 07/11/2013 | US20130177274 Structures formed using monocrystalline silicon and/or other materials for optical and other applications |
| 07/11/2013 | US20130177041 System and method for monitoring in real time the operating state of an igbt device |
| 07/11/2013 | US20130176194 Organic light-emitting display apparatus and method of repairing the same |
| 07/11/2013 | US20130176073 Back-end electrically programmable fuse |
| 07/11/2013 | US20130175901 Nanopiezoelectric generator and method of manufacturing the same |
| 07/11/2013 | US20130175709 Integrated circuit package and method of assembling an integrated circuit package |
| 07/11/2013 | US20130175705 Stress Compensation Layer for 3D Packaging |
| 07/11/2013 | US20130175704 Discrete power transistor package having solderless dbc to leadframe attach |
| 07/11/2013 | US20130175703 Semiconductor device and method of manufacturing semiconductor device |
| 07/11/2013 | US20130175701 Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection |
| 07/11/2013 | US20130175700 Semiconductor die connection system and method |
| 07/11/2013 | US20130175699 Stackable microelectronic package structures |
| 07/11/2013 | US20130175698 Integrated Circuit Constructions Having Through Substrate Vias And Methods Of Forming Integrated Circuit Constructions Having Through Substrate Vias |
| 07/11/2013 | US20130175697 Interlevel Dielectric Stack for Interconnect Structures |
| 07/11/2013 | US20130175696 Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief |
| 07/11/2013 | US20130175694 Packages and Method of Forming the Same |
| 07/11/2013 | US20130175692 Semiconductor device having groove-shaped via-hole |
| 07/11/2013 | US20130175691 Semiconductor device having groove-shaped via-hole |
| 07/11/2013 | US20130175689 Bonding pad and method of making same |
| 07/11/2013 | US20130175687 Package stack device and fabrication method thereof |
| 07/11/2013 | US20130175686 Enhanced Flip Chip Package |
| 07/11/2013 | US20130175685 UBM Formation for Integrated Circuits |
| 07/11/2013 | US20130175683 Semiconductor Device And Bump Formation Process |
| 07/11/2013 | US20130175680 Dielectric material with high mechanical strength |
| 07/11/2013 | US20130175678 Power Semiconductor Module and Manufacturing Method Thereof |
| 07/11/2013 | US20130175677 Integrated Circuit Device With Wire Bond Connections |
| 07/11/2013 | US20130175672 Low temperature layer transfer process using donor structure with material in recesses in transfer layer, semiconductor structures fabricated using such methods |
| 07/11/2013 | US20130175671 Methods for processing a semiconductor wafer, a semiconductor wafer and a semiconductor device |
| 07/11/2013 | US20130175670 Zener diode structure and manufacturing method thereof |
| 07/11/2013 | US20130175665 Thermally stable high-k tetragonal hfo2 layer within high aspect ratio deep trenches |
| 07/11/2013 | US20130175662 Semiconductor material manufacture |
| 07/11/2013 | US20130175660 Dummy Gate Structure for Semiconductor Devices |
| 07/11/2013 | US20130175659 FinFETs with Vertical Fins and Methods for Forming the Same |
| 07/11/2013 | US20130175656 Isolated zener diode |
| 07/11/2013 | US20130175654 Bulk nanohole structures for thermoelectric devices and methods for making the same |
| 07/11/2013 | US20130175644 Spin Torque Transfer Magnetic Tunnel Junction Fabricated with a Composite Tunneling Barrier Layer |
| 07/11/2013 | US20130175640 Stress enhanced mos transistor and methods for fabrication |
| 07/11/2013 | US20130175638 Finfets and the methods for forming the same |
| 07/11/2013 | US20130175637 Device and methods for small trench patterning |
| 07/11/2013 | US20130175632 Reduction of contact resistance and junction leakage |
| 07/11/2013 | US20130175631 Layout to minimize fet variation in small dimension photolithography |
| 07/11/2013 | US20130175630 Replacement gate structure for transistor with a high-k gate stack |
| 07/11/2013 | US20130175629 Device and methods for forming partially self-aligned trenches |
| 07/11/2013 | US20130175628 Electronic device including electrically conductive body for esd protection and related methods |
| 07/11/2013 | US20130175627 Sram integrated circuits and methods for their fabrication |
| 07/11/2013 | US20130175623 Recessed source and drain regions for finfets |
| 07/11/2013 | US20130175622 Electrical isolation structures for ultra-thin semiconductor-on-insulator devices |
| 07/11/2013 | US20130175621 Finfet structure and method for making the same |
| 07/11/2013 | US20130175620 Finfet with fully silicided gate |
| 07/11/2013 | US20130175619 Silicon-on-insulator transistor with self-aligned borderless source/drain contacts |