| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 07/23/2013 | US8492764 Light-emitting device and manufacturing method thereof |
| 07/23/2013 | US8492760 Semiconductor device and method for manufacturing the same |
| 07/23/2013 | US8492756 Semiconductor device and method for manufacturing the same |
| 07/23/2013 | US8492754 Organic light-emitting display panel, display device, and method of manufacturing organic light-emitting display panel |
| 07/23/2013 | US8492753 Directionally recrystallized graphene growth substrates |
| 07/23/2013 | US8492742 Variable resistive element, method for producing the same, and nonvolatile semiconductor memory device including the variable resistive element |
| 07/23/2013 | US8492736 Ozone plenum as UV shutter or tunable UV filter for cleaning semiconductor substrates |
| 07/23/2013 | US8492676 Laser dicing device |
| 07/23/2013 | US8492295 On-chip cooling for integrated circuits |
| 07/23/2013 | US8492294 Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic suppressing region |
| 07/23/2013 | US8492293 High density selective deposition of carbon nanotubes onto a substrate |
| 07/23/2013 | US8492292 Methods of forming oxide layers on substrates |
| 07/23/2013 | US8492291 Formation of gate dielectrics with uniform nitrogen distribution |
| 07/23/2013 | US8492290 Fabrication of silicon oxide and oxynitride having sub-nanometer thickness |
| 07/23/2013 | US8492289 Barrier layer formation for metal interconnects through enhanced impurity diffusion |
| 07/23/2013 | US8492288 Methods of treating semiconductor substrates, methods of forming openings during semiconductor fabrication, and methods of removing particles from over semiconductor substrates |
| 07/23/2013 | US8492287 Substrate processing method |
| 07/23/2013 | US8492286 Method of forming E-fuse in replacement metal gate manufacturing process |
| 07/23/2013 | US8492285 Method for plasma texturing |
| 07/23/2013 | US8492284 Low temperature etchant for treatment of silicon-containing surfaces |
| 07/23/2013 | US8492283 Method and structure for automated inert gas charging in a reticle stocker |
| 07/23/2013 | US8492282 Methods of forming a masking pattern for integrated circuits |
| 07/23/2013 | US8492281 Liquid composition, method of producing silicon substrate, and method of producing liquid discharge head substrate |
| 07/23/2013 | US8492280 Method for simultaneously forming features of different depths in a semiconductor substrate |
| 07/23/2013 | US8492279 Method of controlling critical dimensions of vias in a metallization system of a semiconductor device during silicon-ARC etch |
| 07/23/2013 | US8492278 Method of forming a plurality of spaced features |
| 07/23/2013 | US8492277 Method of polishing a substrate comprising polysilicon and at least one of silicon oxide and silicon nitride |
| 07/23/2013 | US8492276 Chemical mechanical polishing aqueous dispersion and chemical mechanical polishing method |
| 07/23/2013 | US8492275 Method to form uniform silicide by selective implantation |
| 07/23/2013 | US8492274 Metal alloy cap integration |
| 07/23/2013 | US8492273 Method for selective deposition of a semiconductor material |
| 07/23/2013 | US8492272 Passivated through wafer vias in low-doped semiconductor substrates |
| 07/23/2013 | US8492271 Semiconductor device and method of manufacturing the same |
| 07/23/2013 | US8492270 Structure for nano-scale metallization and method for fabricating same |
| 07/23/2013 | US8492269 Hybrid contact structure with low aspect ratio contacts in a semiconductor device |
| 07/23/2013 | US8492267 Pillar interconnect chip to package and global wiring structure |
| 07/23/2013 | US8492266 Semiconductor device having insulating film with surface modification layer and method for manufacturing the same |
| 07/23/2013 | US8492265 Pad bonding employing a self-aligned plated liner for adhesion enhancement |
| 07/23/2013 | US8492264 Method for forming interconnection levels of an integrated circuit |
| 07/23/2013 | US8492263 Protected solder ball joints in wafer level chip-scale packaging |
| 07/23/2013 | US8492262 Direct IMS (injection molded solder) without a mask for forming solder bumps on substrates |
| 07/23/2013 | US8492261 Damascene contacts on III-V CMOS devices |
| 07/23/2013 | US8492260 Processes of forming an electronic device including a feature in a trench |
| 07/23/2013 | US8492259 Method of forming metal gate structure |
| 07/23/2013 | US8492258 Method of manufacturing semiconductor device and substrate processing apparatus |
| 07/23/2013 | US8492257 Semiconductor device with vertical transistor and method for fabricating the same |
| 07/23/2013 | US8492256 Method of manufacturing semiconductor apparatus |
| 07/23/2013 | US8492255 Trenched Schottky diode and method of forming a trenched Schottky diode |
| 07/23/2013 | US8492254 Method of manufacturing semiconductor devices |
| 07/23/2013 | US8492253 Method of forming contacts for a back-contact solar cell |
| 07/23/2013 | US8492252 Three dimensional integration and methods of through silicon via creation |
| 07/23/2013 | US8492251 Method of forming a thin layer structure |
| 07/23/2013 | US8492248 Manufacturing method of semiconductor substrate |
| 07/23/2013 | US8492247 Programmable FETs using Vt-shift effect and methods of manufacture |
| 07/23/2013 | US8492246 Method of manufacturing integrated circuit device |
| 07/23/2013 | US8492245 Methods for making thin layers of crystalline materials |
| 07/23/2013 | US8492243 Method for the production of a semiconductor structure |
| 07/23/2013 | US8492241 Method for simultaneously forming a through silicon via and a deep trench structure |
| 07/23/2013 | US8492240 Solar-cell marking method and solar cell |
| 07/23/2013 | US8492239 Homogeneous porous low dielectric constant materials |
| 07/23/2013 | US8492238 Method and apparatus for fabricating piezoresistive polysilicon by low-temperature metal induced crystallization |
| 07/23/2013 | US8492237 Methods of fabricating a bipolar junction transistor with a self-aligned emitter and base |
| 07/23/2013 | US8492236 Step-like spacer profile |
| 07/23/2013 | US8492235 FinFET with stressors |
| 07/23/2013 | US8492234 Field effect transistor device |
| 07/23/2013 | US8492232 Production of a transistor gate on a multibranch channel structure and means for isolating this gate from the source and drain regions |
| 07/23/2013 | US8492231 Nanoscale variable resistor/electromechanical transistor |
| 07/23/2013 | US8492230 Semiconductor device and method of manufacturing the same |
| 07/23/2013 | US8492229 Method and layout of semiconductor device with reduced parasitics |
| 07/23/2013 | US8492228 Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers |
| 07/23/2013 | US8492227 Method of forming side wall spacers for a semiconductor device |
| 07/23/2013 | US8492226 Trench transistor |
| 07/23/2013 | US8492225 Integrated trench guarded schottky diode compatible with powerdie, structure and method |
| 07/23/2013 | US8492224 Metal control gate structures and air gap isolation in non-volatile memory |
| 07/23/2013 | US8492223 Methods of manufacturing flash memory devices by selective removal of nitrogen atoms |
| 07/23/2013 | US8492222 Method for forming a pixel of an organic electroluminescence device having stacked storage capacitors connecting between power supply and gate electrode |
| 07/23/2013 | US8492221 Method for fabricating power semiconductor device with super junction structure |
| 07/23/2013 | US8492220 Vertically stacked FETs with series bipolar junction transistor |
| 07/23/2013 | US8492219 Semiconductor device manufacturing method |
| 07/23/2013 | US8492218 Removal of an overlap of dual stress liners |
| 07/23/2013 | US8492217 Methods of forming conductive contacts with reduced dimensions |
| 07/23/2013 | US8492216 Semiconductor structure with contact structure and manufacturing method of the same |
| 07/23/2013 | US8492215 Static random access memory (SRAM) cell and method for forming same |
| 07/23/2013 | US8492214 Damascene metal gate and shield structure, methods of manufacture and design structures |
| 07/23/2013 | US8492213 Transistor and method for forming the same |
| 07/23/2013 | US8492210 Transistor, semiconductor device comprising the transistor and method for manufacturing the same |
| 07/23/2013 | US8492208 Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process |
| 07/23/2013 | US8492207 Implementing eFuse circuit with enhanced eFuse blow operation |
| 07/23/2013 | US8492206 Semiconductor device structure and method for manufacturing the same |
| 07/23/2013 | US8492205 Offset geometries for area reduction in memory arrays |
| 07/23/2013 | US8492204 Integrated circuit package-in-package system with wire-in-film encapsulant and method for manufacturing thereof |
| 07/23/2013 | US8492203 Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers |
| 07/23/2013 | US8492201 Semiconductor device and method of forming through vias with reflowed conductive material |
| 07/23/2013 | US8492200 Method for fabricating a semiconductor and semiconductor package |
| 07/23/2013 | US8492199 Reworkable underfills for ceramic MCM C4 protection |
| 07/23/2013 | US8492198 Microelectronic workpieces with stand-off projections and methods for manufacturing microelectronic devices using such workpieces |
| 07/23/2013 | US8492197 Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate |
| 07/23/2013 | US8492196 Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die |
| 07/23/2013 | US8492195 Method for forming stackable non-volatile resistive switching memory devices |
| 07/23/2013 | US8492194 Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell |