Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2013
07/18/2013US20130183835 Low temperature plasma enhanced chemical vapor deposition of conformal silicon carbon nitride and silicon nitride films
07/18/2013US20130183834 Methods and apparatus for processing a substrate
07/18/2013US20130183833 Laser micro/nano processing system and method
07/18/2013US20130183832 Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications
07/18/2013US20130183831 Reducing Substrate Warpage in Semiconductor Processing
07/18/2013US20130183830 Silicon-containing composition for formation of resist underlayer film, which contains organic group containing protected aliphatic alcohol
07/18/2013US20130183829 Methods for increased array feature density
07/18/2013US20130183828 Pattern formation method and guide pattern material
07/18/2013US20130183827 Methods Of Patterning Substrates
07/18/2013US20130183826 Composition for polishing and composition for rinsing
07/18/2013US20130183825 Method for manufacturing damascene structure
07/18/2013US20130183824 Method of fabricating a semiconductor device
07/18/2013US20130183823 Bumping process
07/18/2013US20130183822 Thin film transistor and method of manufacturing trench, metal wire, and thin film transistor array panel
07/18/2013US20130183820 Method for manufacturing silicon carbide semiconductor device
07/18/2013US20130183817 Methods of Reducing Gate Leakage
07/18/2013US20130183816 Method of manufacturing semiconductor device
07/18/2013US20130183815 Methods for depositing group iii-v layers on substrates
07/18/2013US20130183814 Method of depositing a silicon germanium tin layer on a substrate
07/18/2013US20130183813 Method for manufacturing optical semiconductor device
07/18/2013US20130183812 Method for manufacturing electronic parts
07/18/2013US20130183811 Wafer processing method
07/18/2013US20130183810 System and method for manufacturing semiconductor device
07/18/2013US20130183809 Method of fabricating memory device
07/18/2013US20130183808 Memory device and method of fabricating the same
07/18/2013US20130183807 Method of manufacturing a semiconductor apparatus and electronic equipment
07/18/2013US20130183804 Method for fabricating mos device
07/18/2013US20130183803 Method for manufacturing semiconductor structure
07/18/2013US20130183801 Method for manufacturing semiconductor devices
07/18/2013US20130183800 Circuit board structure and fabrication thereof
07/18/2013US20130183798 Method for manufacturing semiconductor devices having gallium nitride epilayers on diamond substrates using intermediate nucleating layer
07/18/2013US20130183797 METHOD FOR PREPARING P-TYPE ZnO-BASED MATERIAL
07/18/2013US20130183780 Method for producing semiconductor optical device
07/18/2013US20130183775 Process and device for producing at least one photonic component
07/18/2013US20130183774 Integrated Circuit Testing Method
07/18/2013US20130183624 Radiation-sensitive resin composition
07/18/2013US20130183131 Dual arm vacuum robot
07/18/2013US20130183122 Wafer transport apparatus
07/18/2013US20130183121 Vacuum processing apparatus
07/18/2013US20130182834 Method and System to Connect Consumers to Information
07/18/2013US20130182490 Static Random Access Memory Cell with Single-Sided Buffer and Asymmetric Construction
07/18/2013US20130182487 Programmable metallization cell with two dielectric layers
07/18/2013US20130182486 Memory cells having a common gate terminal
07/18/2013US20130182484 Word line and power conductor within a metal layer of a memory cell
07/18/2013US20130182305 Optical device having reduced optical leakage
07/18/2013US20130182233 Exposure apparatus and device fabrication method
07/18/2013US20130181808 Metallic silicide resistive thermal sensor and method for manufacturing the same
07/18/2013US20130181360 Integrated circuit connectivity using flexible circuitry
07/18/2013US20130181359 Methods and Apparatus for Thinner Package on Package Structures
07/18/2013US20130181356 Microelectronic devices and methods for manufacturing microelectronic devices
07/18/2013US20130181355 Support Structure for TSV in MEMS Structure
07/18/2013US20130181352 Method of Growing Carbon Nanotubes Laterally, and Lateral Interconnections and Effect Transistor Using the Same
07/18/2013US20130181350 Semiconductor devices with nonconductive vias
07/18/2013US20130181348 Semiconductor device having backside redistribution layers and method for fabricating the same
07/18/2013US20130181347 Bump Pad Structure
07/18/2013US20130181343 Multi-chip package and method of manufacturing the same
07/18/2013US20130181341 Semiconductor package structure and method for manufacturing the same
07/18/2013US20130181340 Semiconductor devices with compliant interconnects
07/18/2013US20130181339 Multi-chip self-alignment assembly which can be used with flip-chip bonding
07/18/2013US20130181338 Package on Package Interconnect Structure
07/18/2013US20130181337 Power Routing with Integrated Decoupling Capacitance
07/18/2013US20130181336 Semiconductor package with improved thermal properties
07/18/2013US20130181334 Connector and resin-sealed semiconductor device
07/18/2013US20130181333 Semiconductor package structure and manufacturing method thereof
07/18/2013US20130181331 Atmospheric-pressure plasma-enhanced chemical vapor deposition
07/18/2013US20130181330 Integrating through substrate vias into middle-of-line layers of integrated circuits
07/18/2013US20130181329 Semiconductor device and process for producing semiconductor device
07/18/2013US20130181327 Epitaxial substrate for semiconductor device, method for manufacturing epitaxial substrate for semiconductor device, and semiconductor device
07/18/2013US20130181326 Multilayer mim capacitor
07/18/2013US20130181325 Through-Assembly Via Modules and Methods for Forming the Same
07/18/2013US20130181323 Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate
07/18/2013US20130181322 Electrical Signal Isolation and Linearity in SOI Structures
07/18/2013US20130181321 SOI Structure and Method for Utilizing Trenches for Signal Isolation and Linearity
07/18/2013US20130181320 Manufacturing Techniques for Workpieces with Varying Topographies
07/18/2013US20130181319 Trench Schottky Barrier Diode and Manufacturing Method Thereof
07/18/2013US20130181317 Semiconductor unit, method of manufacturing the semiconductor unit, solid-state image pickup unit, and electronic apparatus
07/18/2013US20130181304 Methods and apparatus for magnetic sensor having non-conductive die paddle
07/18/2013US20130181300 Control Fin Heights in FinFET Structures
07/18/2013US20130181299 Strain Engineering in Three-Dimensional Transistors Based on Strained Isolation Material
07/18/2013US20130181294 Method for fabrication of an integrated circuit in a technology reduced with respect to a native technology, and corresponding integrated circuit
07/18/2013US20130181293 Diffusion barrier for oppositely doped portions of gate conductor
07/18/2013US20130181292 Local interconnects compatible with replacement gate structures
07/18/2013US20130181291 Silicon oxynitride film and method for forming same, and semiconductor device
07/18/2013US20130181290 Selective Amorphization for Electrical Signal Isolation and Linearity in SOI Structures
07/18/2013US20130181287 High voltage device
07/18/2013US20130181286 High voltage device
07/18/2013US20130181284 Method for Forming Self-Aligned Trench Contacts of Semiconductor Components and A Semiconductor Component
07/18/2013US20130181281 Semiconductor Transistor Having Trench Contacts and Method for Forming Therefor
07/18/2013US20130181279 Sonos structure and manufacturing method thereof
07/18/2013US20130181277 Semiconductor device and method for fabricating thereof
07/18/2013US20130181274 Semiconductor device and method for manufacturing the same
07/18/2013US20130181269 Decoupling capacitor and method of making same
07/18/2013US20130181265 Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer
07/18/2013US20130181264 Semiconductor structure and process thereof
07/18/2013US20130181263 Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure
07/18/2013US20130181262 Performing Treatment on Stressors
07/18/2013US20130181261 Borderless contact structure
07/18/2013US20130181260 Method for forming n-shaped bottom stress liner
07/18/2013US20130181259 Step-like spacer profile
07/18/2013US20130181253 Semiconductor structure and manufacturing method thereof