Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2004
07/08/2004US20040131878 Providing a copper layer over a substrate, copper layer having an exposed copper surface; forming a tantalum layer on copper layer by sputtering
07/08/2004US20040131866 For use as substrate for a semiconductor device
07/08/2004US20040131796 Method of fabricating a protective film by use of vacuum ultraviolet rays
07/08/2004US20040131783 Semiconductor wafer cleaning; size adaptability, minimizing decomposition time;, higher reacting velocity
07/08/2004US20040131782 Preventing disconnections and short circuits; surface pretreating to set contact angle for ink jet droplet
07/08/2004US20040131775 Preventing deformation by adsorbing and embedding contaminant particles; minimizing defects produced by extreme ultraviolet lithography
07/08/2004US20040131774 Increasing surface area, decreasing thickness; high frequency noise reduction; on-chip logic circuit decoupling capacitor for logic circuits, dynamic random access memory storage capacitor
07/08/2004US20040131766 Substrate processing method and apparatus
07/08/2004US20040131763 Methods of forming roughened layers of platinum
07/08/2004US20040131762 Manufacturing of a high-capacitance capacitor
07/08/2004US20040131537 Multilayer ribbon; epitaxial deposits; laser ablation
07/08/2004US20040131461 Substrate conveyer robot
07/08/2004US20040131460 Catch-pin water support for process chamber
07/08/2004US20040131351 Film-processing method and film-processing apparatus
07/08/2004US20040131300 Optical monitoring of thin film deposition
07/08/2004US20040131257 Pattern measurement method, manufacturing method of semiconductor device, pattern measurement apparatus, and program
07/08/2004US20040131246 Micropattern measuring method, micropattern measuring apparatus, and computer-readable recording medium on which a micropattern measuring program is recorded
07/08/2004US20040131099 Process for improving yield of DFB lasers
07/08/2004US20040130965 Chemical dilution system for semiconductor device processing system
07/08/2004US20040130957 Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to dram mosfet array transistor
07/08/2004US20040130955 Magnetic memory, magnetic memory array, method for fabricating a magnetic memory, method for recording in a magnetic memory and method for reading out from a magnetic memory
07/08/2004US20040130950 Electrically erasable programmable logic device
07/08/2004US20040130947 Flash memory with trench select gate and fabrication process
07/08/2004US20040130941 Multibit metal nanocrystal memories and fabrication
07/08/2004US20040130940 Magnetic element utilizing spin transfer and an MRAM device using the magnetic element
07/08/2004US20040130934 NROM memory cell, memory array, related devices and methods
07/08/2004US20040130931 Semiconductor memory device with memory cell having low cell ratio
07/08/2004US20040130849 Layer capacitor element and production process as well as electronic device
07/08/2004US20040130809 Focusing-device for the radiation from a light source
07/08/2004US20040130806 Catadioptric system and exposure device having this system
07/08/2004US20040130727 Surface inspection method and apparatus
07/08/2004US20040130711 Method of detecting mask defects, a computer program and reference substrate
07/08/2004US20040130698 Managing method of exposure apparatus, managing method of mask, exposure method, and manufacturing method of semiconductor device
07/08/2004US20040130697 Reflection preventing film modifying apparatus and reflection preventing film modifying method
07/08/2004US20040130694 Reduced illumination radiation contamination
07/08/2004US20040130693 Lithographic apparatus, optical element and device manufacturing method
07/08/2004US20040130692 Substrate processing apparatus
07/08/2004US20040130690 Alignment system and methods for lithographic systems using at least two wavelengths
07/08/2004US20040130688 Temperature adjustment apparatus, exposure apparatus having the temperature adjustment apparatus, and semiconductor device manufacturing method
07/08/2004US20040130516 Organic light emitting diode display having shield electrodes
07/08/2004US20040130436 Laser-trimmable digital resistor
07/08/2004US20040130434 Method of fabrication of MIMCAP and resistor at same level
07/08/2004US20040130380 Switching circuit device
07/08/2004US20040130372 Semiconductor apparatus
07/08/2004US20040130348 Semiconductor integrated circuit having a plurality of threshold voltages
07/08/2004US20040130344 Systems and methods for testing receiver terminations in integrated circuits
07/08/2004US20040130263 High brightness led and method for producing the same
07/08/2004US20040130073 Manufacturing method and method for operating treatment apparatus
07/08/2004US20040130037 Group III nitride based flip-chip intergrated circuit and method for fabricating
07/08/2004US20040130035 Method of forming copper interconnects
07/08/2004US20040130033 Semiconductor device
07/08/2004US20040130032 by using multiple layers of pre-porous dielectric materials that are made porous subsequent to etching and metal filling of apertures ; Suitable etch differential between the layers can be achieved through the use of certain removable material
07/08/2004US20040130031 modifying carborane material to enable it to be deposited by chemical vapor deposition; used as a semiconductor
07/08/2004US20040130030 Semiconductor device and method for manufacturing same
07/08/2004US20040130029 Conformal lining layers for damascene metallization
07/08/2004US20040130028 Semiconductor device and manufacturing method thereof
07/08/2004US20040130026 Semiconductor device and method of manufacturing the same
07/08/2004US20040130025 Electrode for p-type Group III nitride compound semiconductor and method for producing the same
07/08/2004US20040130024 Semiconductor device package manufacturing method and semiconductor device package manufactured by the method
07/08/2004US20040130023 has bumps that have electrical connection capabilities disposed at the sections of four corners of a semiconductor chip , as well as electrically-non-contact dummy bumps,
07/08/2004US20040130020 Semiconductor device and manufacturing method thereof
07/08/2004US20040130018 Method of manufacturing a low expansion material and semiconductor device using the low expansion material
07/08/2004US20040130017 Stacked layer type semiconductor device and its manufacturing method
07/08/2004US20040130015 Semiconductor apparatus having adhesion layer and semiconductor thin film
07/08/2004US20040130014 Semiconductor device and its manufacturing method
07/08/2004US20040130013 Electronic parts packaging structure and method of manufacturing the same
07/08/2004US20040130012 uses a contact system in which the ends of the contact elements of the integrated circuit and substrate are not firmly connected to one another, but are placed one on top of the other, while being under a specific pressure
07/08/2004US20040130009 Method for maintaining solder thickness in flipchip attach packaging processes
07/08/2004US20040130006 Method and structure for ultra-thin film soi isolation
07/08/2004US20040130005 Underlayer for polysilicon TFT
07/08/2004US20040130004 Semiconductor device whose semiconductor chip has chamfered backside surface edges and method of manufacturing the same
07/08/2004US20040130003 Fine line circuitization
07/08/2004US20040130002 Gallium nitride material devices and methods of forming the same
07/08/2004US20040130001 arranging a plurality of dice in a semiconductor wafer such that there is a separation region between each neighboring die of the semiconductor wafer; trenches are etched in the separation region of the wafer, which is then fractured into pieces
07/08/2004US20040129999 Semiconductor device and method of manufacturing the same
07/08/2004US20040129998 Semiconductor device with a cavity therein and a method of manufacturing the same
07/08/2004US20040129997 Semiconductor apparatus and method for manufacturing the same
07/08/2004US20040129995 Semiconductor chip with gate dielectrics for high-performance and low-leakage applications
07/08/2004US20040129990 reduces dark current by protecting the surface of the photodiode from the blanket dry etching using spacer etching barrier film, thus improves the optical properties for short wavelength light using a spacer forming insulation layer residual
07/08/2004US20040129988 Use of indium to define work function of p-type doped polysilicon of polysilicon germanium
07/08/2004US20040129987 Ferroelectric composite material, method of making same and memory utilizing same
07/08/2004US20040129986 miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and improving the yield
07/08/2004US20040129985 Method for operating n-channel electrically erasable programmable logic device
07/08/2004US20040129982 Semiconductor device and manufacturing method
07/08/2004US20040129981 Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad and integrated circuit devices formed thereby
07/08/2004US20040129980 Semiconductor device with resistor element
07/08/2004US20040129979 CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture
07/08/2004US20040129978 Manufacturing method of thin-film transistor, thin-film transistor sheet, and electric circuit
07/08/2004US20040129977 SOI substrate and semiconductor integrated circuit device
07/08/2004US20040129976 Bladed silicon-on-insulator semiconductor devices and method of making
07/08/2004US20040129975 Semiconductor device and method for manufacturing the same
07/08/2004US20040129974 System with meshed power and signal buses on cell array
07/08/2004US20040129973 Power semiconductor device
07/08/2004US20040129972 having memory region in which memory cell array is formed of non-volatile memory devices arranged in matrix of rows and columns, each.device has word gate formed above semiconductor layer with insulating layer interposed, impurity layer, controller
07/08/2004US20040129971 Method and apparatus for dual conduction analog programming
07/08/2004US20040129970 Semiconductor device and method for fabricating the same
07/08/2004US20040129969 Control of high -k gate dielectric film composition profile for property optimization
07/08/2004US20040129968 diffusion barrier layer comprising ternary compound elements formed on a substrate comprising ruthenium, titanium and nitrogen; capacitor comprising a bottom electrode formed on oxygen diffusion barrier layer; dielectric layer
07/08/2004US20040129967 first insulation layer pattern having a first contact hole is formed on a substrate, a contact plug for the bottom electrode is formed in contact hole, second insulation layer is formed; prevents formation of bridge between adjacent contact plugs
07/08/2004US20040129966 Metal-metal capacitor array