Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2004
07/20/2004US6764953 Electronic device, and method of patterning a first layer
07/20/2004US6764952 Systems and methods to retard copper diffusion and improve film adhesion for a dielectric barrier on copper
07/20/2004US6764951 Method for forming nitride capped Cu lines with reduced hillock formation
07/20/2004US6764950 Fabrication method for semiconductor integrated circuit device
07/20/2004US6764949 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
07/20/2004US6764948 Method of manufacturing a semiconductor device and the semiconductor device manufactured by the method
07/20/2004US6764947 Method for reducing gate line deformation and reducing gate line widths in semiconductor devices
07/20/2004US6764946 Method of controlling line edge roughness in resist films
07/20/2004US6764945 Method of manufacturing a multilayer metallization structure with non-directional sputtering method
07/20/2004US6764944 Low viscosity antireflectivity pattern
07/20/2004US6764943 Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers
07/20/2004US6764942 Re-oxidation process of semiconductor device
07/20/2004US6764941 Bit line landing pad and borderless contact on bit line stud with localized etch stop layer and manufacturing method thereof
07/20/2004US6764940 Method for depositing a diffusion barrier for copper interconnect applications
07/20/2004US6764939 Semiconductor device and method of manufacturing the same
07/20/2004US6764938 Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof
07/20/2004US6764937 Solder on a sloped surface
07/20/2004US6764935 Stereolithographic methods for fabricating conductive elements
07/20/2004US6764934 Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random
07/20/2004US6764933 Stereolithographically fabricated conductive elements, semiconductor device components and assemblies including such conductive elements, and methods
07/20/2004US6764932 Single step pendeo- and lateral epitaxial overgrowth of group III-nitride epitaxial layers with group III-nitride buffer layer and resulting structures
07/20/2004US6764931 Semiconductor package, method of manufacturing the same, and semiconductor device
07/20/2004US6764930 Method and structure for modular, highly linear MOS capacitors using nitrogen implantation
07/20/2004US6764929 Method and system for providing a contact hole in a semiconductor device
07/20/2004US6764928 Method of manufacturing an El display device
07/20/2004US6764927 Chemical vapor deposition (CVD) method employing wetting pre-treatment
07/20/2004US6764926 Method for obtaining high quality InGaAsN semiconductor devices
07/20/2004US6764925 Semiconductor device manufacturing system and electron beam exposure apparatus
07/20/2004US6764923 Silicon substrate; dielectric interface; metal silicide layer
07/20/2004US6764922 Method of formation of an oxynitride shallow trench isolation
07/20/2004US6764921 Semiconductor device and method for fabricating the same
07/20/2004US6764920 Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devices
07/20/2004US6764919 Method for providing a dummy feature and structure thereof
07/20/2004US6764918 Structure and method of making a high performance semiconductor device having a narrow doping profile
07/20/2004US6764917 SOI device with different silicon thicknesses
07/20/2004US6764916 Manufacturing method for semiconductor device
07/20/2004US6764915 Method of forming a MIM capacitor structure
07/20/2004US6764914 Method of forming a high K metallic dielectric layer
07/20/2004US6764913 Method for controlling an emitter window opening in an HBT and related structure
07/20/2004US6764912 Passivation of nitride spacer
07/20/2004US6764911 Multiple etch method for fabricating spacer layers
07/20/2004US6764910 Structure of semiconductor device and method for manufacturing the same
07/20/2004US6764909 Structure and method of MOS transistor having increased substrate resistance
07/20/2004US6764908 Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents
07/20/2004US6764907 Method of fabricating self-aligned silicon carbide semiconductor devices
07/20/2004US6764906 Method for making trench mosfet having implanted drain-drift region
07/20/2004US6764905 Method of manufacturing a scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate
07/20/2004US6764904 Trenched gate non-volatile semiconductor method with the source/drain regions spaced from the trench by sidewall dopings
07/20/2004US6764903 Dual hard mask layer patterning method
07/20/2004US6764902 Method of manufacturing semiconductor device
07/20/2004US6764901 Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
07/20/2004US6764900 Method of fabricating an X-ray detector array element
07/20/2004US6764899 Method for fabricating semiconductor device
07/20/2004US6764898 Implantation into high-K dielectric material after gate etch to facilitate removal
07/20/2004US6764896 Semiconductor manufacturing method including patterning a capacitor lower electrode by chemical etching
07/20/2004US6764895 Integrated circuits; vapor deposition
07/20/2004US6764893 Method for reducing a parasitic capacitance of a semiconductive memory cell using metal mask for sidewall formation
07/20/2004US6764892 Device and method of low voltage SCR protection for high voltage failsafe ESD applications
07/20/2004US6764890 Method of adjusting the threshold voltage of a mosfet
07/20/2004US6764889 Methods of forming vertical mosfets having trench-based gate electrodes within deeper trench-based source electrodes
07/20/2004US6764888 Method of producing nitride-based heterostructure devices
07/20/2004US6764887 Method of forming a thin film transistor on a transparent plate
07/20/2004US6764886 Manufacturing method of semiconductor device
07/20/2004US6764885 Method of fabricating transistor device
07/20/2004US6764884 Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
07/20/2004US6764883 Amorphous and polycrystalline silicon nanolaminate
07/20/2004US6764882 Two-stage transfer molding method to encapsulate MMC module
07/20/2004US6764879 Semiconductor wafer, semiconductor device, and method for manufacturing the same
07/20/2004US6764878 Method of manufacturing a resin encapsulated semiconductor device to provide a vent hole in a base substrate
07/20/2004US6764877 Method of dissipating static electric charge from a chip assembly during a manufacturing operation
07/20/2004US6764876 Stress shield for microelectronic dice
07/20/2004US6764875 Method of and apparatus for sealing an hermetic lid to a semiconductor die
07/20/2004US6764873 Semiconductor wafer including a low dielectric constant thermosetting polymer film and method of making same
07/20/2004US6764871 Method for fabricating a nitride semiconductor device
07/20/2004US6764867 Reticle option layer detection method
07/20/2004US6764865 Semiconductor memory device including magneto resistive element and method of fabricating the same
07/20/2004US6764864 BST on low-loss substrates for frequency agile applications
07/20/2004US6764863 Memory-storage node and the method of fabricating the same
07/20/2004US6764862 Method of forming ferroelectric random access memory device
07/20/2004US6764812 Plasma deposited selective wetting material
07/20/2004US6764811 Pattern formation method
07/20/2004US6764810 Blanket depositing a photosensitive resinous layer to fill via opening in substrate; partially removing photosensitive resinous layer to form filled via plug; photo-curing via plug such that activating light source causes polymer crosslinking
07/20/2004US6764808 Photolithographic exposing with two different wavelengths, the first wavelength is shorter than the second wavelength, achieve smaller resolution; polymerizing arylalkoxysilane compound to polysiloxanes
07/20/2004US6764806 Over-coating composition for photoresist, and processes for forming photoresist patterns using the same
07/20/2004US6764794 Used for focus monitoring that measures the position of an exposed surface in an optical system in order to adjust focus of optical image on exposed surface
07/20/2004US6764792 Halftone phase shift photomask and blanks for halftone phase shift photomask for producing it
07/20/2004US6764774 Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same
07/20/2004US6764773 Heat-dissipating substrate, method for making the same, and semiconductor device including the same
07/20/2004US6764718 Method for forming thin film from electrically insulating resin composition
07/20/2004US6764712 Method for producing high surface area foil electrodes
07/20/2004US6764606 Method and apparatus for plasma processing
07/20/2004US6764585 Electronic device manufacturing method
07/20/2004US6764575 Magnetron plasma processing apparatus
07/20/2004US6764573 Wafer thinning techniques
07/20/2004US6764572 Apparatus and method for semiconductor wafer etching
07/20/2004US6764552 Supercritical solutions for cleaning photoresist and post-etch residue from low-k materials
07/20/2004US6764551 Process for removing dopant ions from a substrate
07/20/2004US6764546 Apparatus and method for growth of a thin film
07/20/2004US6764537 Copper metal precursor
07/20/2004US6764392 Wafer polishing method and wafer polishing device