Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2004
07/20/2004US6765845 Hierarchical word line scheme with decoded block selecting signals and layout method of the same
07/20/2004US6765844 Semiconductor memory device having a hierarchical I/O structure
07/20/2004US6765827 Method and system for detecting defective material surrounding flash memory cells
07/20/2004US6765821 Magnetic memory
07/20/2004US6765815 Semiconductor memory device having a main word-line layer disposed above a column selection line layer
07/20/2004US6765814 Semiconductor memory device
07/20/2004US6765778 Integrated vertical stack capacitor
07/20/2004US6765773 ESD protection for a CMOS output stage
07/20/2004US6765772 Electrostatic discharge protection device
07/20/2004US6765729 Catadioptric reduction lens
07/20/2004US6765717 Preferred crystal orientation optical elements from cubic materials
07/20/2004US6765712 Lithographic apparatus, device manufacturing method, and device manufactured thereby
07/20/2004US6765673 Pattern forming method and light exposure apparatus
07/20/2004US6765666 System and method for inspecting bumped wafers
07/20/2004US6765652 Forming thermally curable materials on a support structure in an electronic device
07/20/2004US6765649 Exposure apparatus and method
07/20/2004US6765641 Display device
07/20/2004US6765630 Display panel
07/20/2004US6765549 Active matrix display with pixel memory
07/20/2004US6765466 Magnetic field generator for magnetron plasma
07/20/2004US6765454 Semiconductor device
07/20/2004US6765434 Semiconductor integrated circuit device
07/20/2004US6765429 Semiconductor integrated circuit with leak current cut-off circuit
07/20/2004US6765427 Method and apparatus for bootstrapping a programmable antifuse circuit
07/20/2004US6765408 Device and method with generic logic blocks
07/20/2004US6765401 Semiconductor testing apparatus for conducting conduction tests
07/20/2004US6765398 Conductive material for integrated circuit fabrication
07/20/2004US6765397 Apparatus and method for testing land grid array modules
07/20/2004US6765303 FinFET-based SRAM cell
07/20/2004US6765297 Semiconductor device and wiring forming method in semiconductor device
07/20/2004US6765295 Multiplexing system and method for crossing signals on a single metal layer of an integrated circuit
07/20/2004US6765294 Semiconductor device including dual-damascene structure and method for manufacturing the same
07/20/2004US6765293 Electrode structure of a carrier substrate of a semiconductor device
07/20/2004US6765292 Contact structure for semiconductor device
07/20/2004US6765290 Arrangement for back-biasing multiple integrated circuit substrates at maximum supply voltage among all circuits
07/20/2004US6765289 Reinforcement material for silicon wafer and process for producing IC chip using said material
07/20/2004US6765283 Semiconductor device with multi-layer interlayer dielectric film
07/20/2004US6765281 Employs multiple polysilicon films
07/20/2004US6765280 Local oxidation of a sidewall sealed shallow trench for providing isolation between devices of a substrate
07/20/2004US6765279 Membrane 3D IC fabrication
07/20/2004US6765277 Aluminum metal or alloy conductor with noble metal passivation layer
07/20/2004US6765276 Bottom antireflection coating color filter process for fabricating solid state image sensors
07/20/2004US6765274 Semiconductor device having a built-in contact-type sensor and manufacturing method of such a semiconductor device
07/20/2004US6765273 Device structure and method for reducing silicide encroachment
07/20/2004US6765272 Semiconductor device
07/20/2004US6765271 Method for manufacturing non-volatile semiconductor memory and non-volatile semiconductor memory manufactured thereby
07/20/2004US6765270 Thin film transistor array gate electrode for liquid crystal display device
07/20/2004US6765269 Conformal surface silicide strap on spacer and method of making same
07/20/2004US6765268 Multiple transistors having a common gate pad between first group of drains and second group of drains
07/20/2004US6765267 Pixel structure
07/20/2004US6765265 System and method for manufacturing a thin film transistor
07/20/2004US6765264 Method of fabricating power rectifier device to vary operating parameters and resulting device
07/20/2004US6765263 Semiconductor device and method for fabricating the same
07/20/2004US6765261 Semiconductor device comprising a non-volatile memory
07/20/2004US6765260 Flash memory with self-aligned split gate and methods for fabricating and for operating the same
07/20/2004US6765259 Non-volatile memory transistor array implementing “H” shaped source/drain regions and method for fabricating same
07/20/2004US6765258 Stack-gate flash memory cell structure and its contactless flash memory arrays
07/20/2004US6765257 Implanted vertical source-line under straight stack for flash eprom
07/20/2004US6765256 Semiconductor device
07/20/2004US6765255 Increased capacitance
07/20/2004US6765254 Structure and method for preventing UV radiation damage and increasing data retention in memory cells
07/20/2004US6765253 Semiconductor memory device
07/20/2004US6765252 Preventing leakage current due to punch through without need of ion injection layer
07/20/2004US6765251 Semiconductor device having interconnection structure
07/20/2004US6765250 Self-aligned, trenchless mangetoresitive random-access memory (MRAM) structure with sidewall containment of MRAM structure
07/20/2004US6765249 Thin-film transistors formed on a flexible substrate
07/20/2004US6765248 Field effect transistor and fabrication method
07/20/2004US6765247 Integrated circuit with a MOS structure having reduced parasitic bipolar transistor action
07/20/2004US6765246 Solid-state imaging device with multiple impurity regions and method for manufacturing the same
07/20/2004US6765244 III nitride film and a III nitride multilayer
07/20/2004US6765243 HBT having a controlled emitter window opening
07/20/2004US6765242 Npn double heterostructure bipolar transistor with ingaasn base region
07/20/2004US6765241 Group III nitride semiconductor device of field effect transistor type having reduced parasitic capacitances
07/20/2004US6765240 Bulk single crystal gallium nitride and method of making same
07/20/2004US6765236 Optical device and method for manufacturing the same, and electronic apparatus
07/20/2004US6765233 Semiconductor substrate, light emitting device, and method for producing the same
07/20/2004US6765231 Semiconductor device and its manufacturing method
07/20/2004US6765229 Method for producing semiconductor device
07/20/2004US6765227 Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding
07/20/2004US6765222 Detection of motive force applied to transport box mounted on a fims system
07/20/2004US6765219 Hybrid scanning system and methods for ion implantation
07/20/2004US6765218 Lithographic projection apparatus with positioning system for use with reflectors
07/20/2004US6765204 Microstructured pattern inspection method
07/20/2004US6765178 Employs reflection; efficient; contaminate free
07/20/2004US6765175 Laser irradiation apparatus, laser irradiation method, and manufacturing method for a semiconductor device
07/20/2004US6765001 Mixture with penetration intensifiers, solvents and emulsifiers
07/20/2004US6764967 Method for forming low thermal budget sacrificial oxides
07/20/2004US6764966 Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric
07/20/2004US6764965 The pre-wetting process being performed on the adhesion promoter layer to enhance the coating capability of the low-k dielectric layer, and thus improve the coating quality
07/20/2004US6764964 Method for forming patterns of a semiconductor device
07/20/2004US6764963 Manufacturing method of semiconductor devices
07/20/2004US6764962 Removing the native oxide layer via dipping in buffered oxide etching solution (hydrogen fluoride or ammonium fluoride), oxidizing nitride layer, then annealing oxynitride layer; dielectrics; improving semiconductor performance
07/20/2004US6764961 Method of forming a metal gate electrode
07/20/2004US6764960 Manufacture of composite oxide film and magnetic tunneling junction element having thin composite oxide film
07/20/2004US6764959 Thermal compensation method for forming semiconductor integrated circuit microelectronic fabrication
07/20/2004US6764958 Method of depositing dielectric films
07/20/2004US6764957 Method for forming contact or via plug
07/20/2004US6764956 Methods of treating dielectric materials
07/20/2004US6764955 Semiconductor device having a contact window and fabrication method thereof
07/20/2004US6764954 Application of alignment marks to wafer