| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 09/13/2005 | US6942548 Polishing method using an abrading plate |
| 09/13/2005 | US6942543 equipped with a film-thickness monitor for monitoring a film thickness of a thin film on a substrate to be polished; high accuracy and reliability |
| 09/13/2005 | US6942541 Polishing apparatus |
| 09/13/2005 | US6942157 Data processing system and data processing method |
| 09/13/2005 | US6941957 Method and apparatus for pretreating a substrate prior to electroplating |
| 09/13/2005 | US6941956 Substrate treating method and apparatus |
| 09/13/2005 | US6941940 Wire saw and process for slicing multiple semiconductor ingots |
| 09/13/2005 | US6941792 Surface inspection system |
| 09/09/2005 | WO2005083799A1 Process for manufacturing photovoltaic cells |
| 09/09/2005 | WO2005083796A1 Semiconductor device and method for manufacturing same |
| 09/09/2005 | WO2005083795A1 Method for manufacturing semiconductor device and plasma oxidation method |
| 09/09/2005 | WO2005083794A2 High voltage pmos transistor |
| 09/09/2005 | WO2005083793A1 Nitride heterojunction transistors having charge-transfer induced energy barriers and methods of fabricating the same |
| 09/09/2005 | WO2005083785A1 System comprising an electrical component and an electrical connecting lead for said component, and method for the production of said system |
| 09/09/2005 | WO2005083782A1 Vertical eeprom nrom memory devices |
| 09/09/2005 | WO2005083781A1 Folded node trench capacitor |
| 09/09/2005 | WO2005083780A2 Cmos silicide metal gate integration |
| 09/09/2005 | WO2005083779A1 Rear-coated thin semiconductor chip, and method for the production thereof |
| 09/09/2005 | WO2005083778A1 Methods of fabricating interconnects for semiconductor components |
| 09/09/2005 | WO2005083777A1 Methods and apparatuses promoting adhesion of dielectric barrier film to copper |
| 09/09/2005 | WO2005083776A1 Integrated circuit chips utilizing carbon nanotube composite interconnection vias |
| 09/09/2005 | WO2005083775A1 FORMATION OF PATTERNED SILICON-ON-INSULATOR (SOI)/SILICON-ON-NOTHING (SON) COMPOSITE STRUCTURE BY POROUS Si ENGINEERING |
| 09/09/2005 | WO2005083774A1 Method of making a small substrate compatible for processing |
| 09/09/2005 | WO2005083773A1 Probe card, and method of producing the same |
| 09/09/2005 | WO2005083772A1 Anisotropic conduction connecting method and anisotropic conduction adhesive film |
| 09/09/2005 | WO2005083771A1 Assembly of a semiconductor die attached to substrate with oxazoline derivative bearing an electron donor or acceptor functionality |
| 09/09/2005 | WO2005083770A1 Semiconductor device of high breakdown voltage and manufacturing method thereof |
| 09/09/2005 | WO2005083769A1 Semiconductor device and method of manufacturing a semiconductor device |
| 09/09/2005 | WO2005083768A1 A method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor |
| 09/09/2005 | WO2005083767A1 Semiconductor device |
| 09/09/2005 | WO2005083766A1 Substrate processing device |
| 09/09/2005 | WO2005083765A1 Semiconductor device |
| 09/09/2005 | WO2005083764A1 Production method for semiconductor device and semiconductor device |
| 09/09/2005 | WO2005083763A1 Wafer transcription method |
| 09/09/2005 | WO2005083762A1 Gate electrode dopant activation method for semiconductor manufacturing |
| 09/09/2005 | WO2005083761A1 Ohmic electrode structure of nitride semiconductor device |
| 09/09/2005 | WO2005083760A1 Substrate processing equipment and semiconductor device manufacturing method |
| 09/09/2005 | WO2005083759A1 Exposure system, and production method for device having fine pattern |
| 09/09/2005 | WO2005083758A1 Stage apparatus and projection exposure apparatus |
| 09/09/2005 | WO2005083757A1 Method for separating resist film and rework process |
| 09/09/2005 | WO2005083756A1 Pre-measurement processing method, exposure system and substrate processing equipment |
| 09/09/2005 | WO2005083755A1 Photoresist film removing device and method |
| 09/09/2005 | WO2005083754A1 Gas supply integration unit |
| 09/09/2005 | WO2005083753A1 Semiconductor treating device |
| 09/09/2005 | WO2005083752A2 Contaminant reducing support system |
| 09/09/2005 | WO2005083751A2 Semiconductor device and method using nanotube contacts |
| 09/09/2005 | WO2005083749A1 Test system with integrated substrate transfer module |
| 09/09/2005 | WO2005083748A1 Device for singulating and bonding semiconductor chips, and singulating and bonding method |
| 09/09/2005 | WO2005083726A1 Thin film ferroelectric composites, method of making and capacitor comprising the same |
| 09/09/2005 | WO2005083524A2 Method for aligning the surface of a substrate |
| 09/09/2005 | WO2005083523A1 Microelectronic cleaning composition containing halogen oxygen acids, salts and derivatives thereof |
| 09/09/2005 | WO2005083522A1 Pattern forming process |
| 09/09/2005 | WO2005083519A2 Methods of patterning a surface using single and multilayer molecular films |
| 09/09/2005 | WO2005083515A1 Process for fabricating semiconductor device and method for generating mask pattern data |
| 09/09/2005 | WO2005083513A2 Composite patterning with trenches |
| 09/09/2005 | WO2005083407A1 Surface inspection using a non-vibrating contact potential probe |
| 09/09/2005 | WO2005083341A1 Silicon layer for uniformizing temperature during photo-annealing |
| 09/09/2005 | WO2005083294A1 Pneumatic spring apparatus, vibration-proof apparatus, stage apparatus and exposure apparatus |
| 09/09/2005 | WO2005083159A2 Apparatus adapted for membrane mediated electropolishing |
| 09/09/2005 | WO2005083152A1 Method for forming copper film |
| 09/09/2005 | WO2005083148A1 Sputtering target with few surface defects and method for processing surface thereof |
| 09/09/2005 | WO2005083147A1 Process for producing film of liquid crystal polymer |
| 09/09/2005 | WO2005083145A2 Vapor deposition source with minimized condensation effects |
| 09/09/2005 | WO2005083138A1 Ni-Pt ALLOY AND TARGET COMPRISING THE ALLOY |
| 09/09/2005 | WO2005082976A1 Polymer and process for producing the same, composition for forming insulating film, and insulating film and method of forming the same |
| 09/09/2005 | WO2005082956A1 Styrene derivative, styrene polymer, photosensitive resin composition, and method for forming pattern |
| 09/09/2005 | WO2005082774A2 Method for making a planar cantilever mems switch |
| 09/09/2005 | WO2005082751A1 Substrate carrying in/out device and method of carrying in/out substrate |
| 09/09/2005 | WO2005082574A1 Methods and apparatuses for electrochemical-mechanical polishing |
| 09/09/2005 | WO2005082122A2 Method of making a semiconductor device using treated photoresist |
| 09/09/2005 | WO2005081798A2 Twin eeprom memory transistors with subsurface stepped floating gates |
| 09/09/2005 | WO2005081769A2 Nor-type channel-program channel-erase contactless flash memory on soi |
| 09/09/2005 | WO2005081768A2 Schottky-barrier tunneling transistor |
| 09/09/2005 | WO2005081757A2 A novel thin laminate as embedded capacitance material in printed circuit boards |
| 09/09/2005 | WO2005081750A2 Group iii-nitride based led having a transparent current spreading layer |
| 09/09/2005 | WO2005081748A2 Semiconductor structure having strained semiconductor and method therefor |
| 09/09/2005 | WO2005081702A2 Integrated getter area for wafer level encapsulated microelectromechanical systems |
| 09/09/2005 | WO2005081618A2 Method for improving heat dissipation in encapsulated electronic components |
| 09/09/2005 | WO2005066386A3 A method and apparatus for forming a high quality low temperature silicon nitride layer |
| 09/09/2005 | WO2005055290A3 Method of fabricating a strained semiconductor-on-insulator substrate |
| 09/09/2005 | WO2005050710A3 Optical device for led-based lamp |
| 09/09/2005 | WO2005049887A3 Methods for the deposition of silver oxide films and patterned films |
| 09/09/2005 | WO2005045904A3 Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation |
| 09/09/2005 | WO2005041273A3 Method for reducing parasitic couplings in circuits |
| 09/09/2005 | WO2005041252B1 SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK |
| 09/09/2005 | WO2005022249A3 Laser thermal processing with laser diode radiation |
| 09/09/2005 | WO2005017972A3 Method for microfabricating structures using silicon-on-insulator material |
| 09/09/2005 | WO2005010926A3 Procede de fabrication de film conducteur anisotrope |
| 09/09/2005 | WO2004111659A3 Methods and apparatus for packaging integrated circuit devices |
| 09/09/2005 | WO2004102274A3 Use of spin-on, photopatternable, interplayer dielectric materials and intermediate semiconductor device structure utilizing the same |
| 09/09/2005 | WO2004099792A3 Planarizing and testing of bga packages |
| 09/09/2005 | WO2004088760A3 Led power package |
| 09/09/2005 | WO2004088715A3 Tapered structure for providing coupling between external optical device and planar optical waveguide and method of forming the same |
| 09/09/2005 | WO2004079794A3 Trench power mosfet with planarized gate bus |
| 09/09/2005 | WO2004070850A3 Improved photovoltaic cell and method of production thereof |
| 09/09/2005 | WO2004064152A3 Modular construction component with encapsulation |
| 09/09/2005 | CA2554942A1 Nitride heterojunction transistors having charge-transfer induced energy barriers and methods of fabricating the same |
| 09/08/2005 | US20050198604 Semiconductor integrated circuit including standard cell, standard cell layout design method, and layout design software product stored in computer-readable recording medium |
| 09/08/2005 | US20050198600 Layout verifying device verifying an interconnection layout |
| 09/08/2005 | US20050198594 Method of designing semiconductor integrated circuit, designing apparatus, and inspection apparatus |