Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2005
09/01/2005WO2005081065A1 Light-sensitive substrate and method for patterning
09/01/2005WO2005081064A1 Bilayer laminated film for bump formation and method of bump formation
09/01/2005WO2005081063A1 Resist laminate used for immersion lithography
09/01/2005WO2005081055A1 Double layer transparent conductor scheme having improved etching properties for transparent electrodes in electro-optic displays
09/01/2005WO2005081034A1 Two-dimensional light modulation device, exposure apparatus, and exposure method
09/01/2005WO2005081003A1 Dual feedback control system for maintaining the temperature of an ic-chip near a set-point
09/01/2005WO2005080950A1 Establishing correspondence and traceability between wafers and solar cells
09/01/2005WO2005080645A2 Diamond structure separation
09/01/2005WO2005080629A2 SILICON COMPOUNDS FOR PRODUCING SiO2-CONTAINING INSULATING LAYERS ON CHIPS
09/01/2005WO2005080505A1 Polyimidesiloxane solution composition
09/01/2005WO2005080474A1 Polymer, photoresist composition containing the polymer, and method of forming resist pattern
09/01/2005WO2005080473A1 Polymer compound, photoresist composition containing such polymer compound, and method for forming resist pattern
09/01/2005WO2005080306A1 Fluorine-containing cyclic compound, fluorine-containing polymer compound, resist material using same and method for forming pattern
09/01/2005WO2005080007A1 Substrate processing apparatus and method
09/01/2005WO2005079498A2 Continuously varying offset mark and methods of determining overlay
09/01/2005WO2005079476A2 Method of dry plasma etching semiconductor materials
09/01/2005WO2005079472A2 Dry etching process for compound semiconductors
09/01/2005WO2005079454A2 Polymer via etching process
09/01/2005WO2005079400A2 Buried guard ring and radiation hardened isolation structures and fabrication methods
09/01/2005WO2005079366A2 Complimentary nitride transistors vertical and common drain
09/01/2005WO2005079318A2 Methods of forming doped and un-doped strained semiconductor and semiconductor films by gas-cluster ion irradiation
09/01/2005WO2005079308A2 One dimensional nanostructures for vertical heterointegration on a silicon platform and method for making same
09/01/2005WO2005079293A2 Integrated iii-nitride power devices
09/01/2005WO2005079198A2 Wafer bonded virtual substrate and method for forming the same
09/01/2005WO2005065273A3 System and method for self-leveling heat sink for multiple height devices
09/01/2005WO2005062371A3 Plastic lead frames utilizing reel-to-reel processing
09/01/2005WO2005055289A3 Bipolar complementary semiconductor device
09/01/2005WO2005038938A3 Adhesive bonding with low temperature grown amorphous or polycrystalline compound semiconductors
09/01/2005WO2005038084A3 Selective self-initiating electroless capping of copper with cobalt-containing alloys
09/01/2005WO2005036650A3 Insulated gate type semiconductor device and manufacturing method thereof
09/01/2005WO2005031841A3 Methods of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition
09/01/2005WO2005029504A3 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
09/01/2005WO2005024903A3 Method and structure for improving the gate resistance of a closed cell trench power mosfet
09/01/2005WO2005009089A3 Plasma processing apparatus
09/01/2005WO2005001904A3 Method of forming freestanding semiconductor layer
09/01/2005WO2004109794B1 Coiled circuit device and method of making the same
09/01/2005WO2004077515A3 Apparatus and method for delivery of reactive chemical precursors to the surface to be treated
09/01/2005WO2004059699A3 System and method for on-the-fly eccentricity recognition
09/01/2005WO2003071008A3 Methods of and apparatus for making high aspect ratio microelectromechanical structures
09/01/2005US20050193364 Pattern forming method and semiconductor device manufactured by using said pattern forming method
09/01/2005US20050193362 Multi-layer overlay measurement and correction technique for IC manufacturing
09/01/2005US20050193354 Method of extraction of wire capacitances in LSI device having diagonal wires and extraction program for same
09/01/2005US20050193300 Semiconductor integrated circuit detecting glitch noise and test method of the same
09/01/2005US20050193294 Wireless no-touch testing of integrated circuits
09/01/2005US20050193293 Semiconductor device capable of performing test at actual operating frequency
09/01/2005US20050193013 Method for evaluating semiconductor device
09/01/2005US20050192787 Simulation apparatus and method of designing semiconductor integrated circuit
09/01/2005US20050192700 Method and system for controlling a product parameter of a circuit element
09/01/2005US20050192699 Temperature-sensing wafer position detection system and method
09/01/2005US20050192409 Polymers of polycyclic olefins having a polyhedral oligosilsesquioxane pendant group and uses thereof
09/01/2005US20050192364 Polyhedral oligomeric silsesquioxanes and metallized polyhedral oligomeric silsesquioxanes as coatings, composites and additives
09/01/2005US20050191952 Cleaning sheet for probe needles
09/01/2005US20050191949 Polishing apparatus
09/01/2005US20050191942 CMP apparatus and process sequence method
09/01/2005US20050191911 Transistor structure with minimized parasitics and method of fabricating the same
09/01/2005US20050191874 Inset mechanism for electronic assemblies
09/01/2005US20050191866 Semiconductor devices and methods for depositing a dielectric film
09/01/2005US20050191865 Treatment of a dielectric layer using supercritical CO2
09/01/2005US20050191864 Magenta toner and method for producing same
09/01/2005US20050191863 Semiconductor device contamination reduction in a fluorinated oxide deposition process
09/01/2005US20050191862 Air gap interconnect structure and method of manufacture
09/01/2005US20050191861 Using supercritical fluids and/or dense fluids in semiconductor applications
09/01/2005US20050191860 Method for forming semiconductor device
09/01/2005US20050191859 Method of evaluating film thickness, method of detecting polishing terminal, and device-manufacturing apparatus
09/01/2005US20050191858 Substrate processing method and apparatus
09/01/2005US20050191857 Capping layer for a semiconductor device and a method of fabrication
09/01/2005US20050191856 Method of forming high aspect ratio structures
09/01/2005US20050191855 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process
09/01/2005US20050191854 Process for purification of germane
09/01/2005US20050191853 Method of manufacturing semiconductor device
09/01/2005US20050191852 Method for manufacturing semiconductor device
09/01/2005US20050191851 Barrier metal cap structure on copper lines and vias
09/01/2005US20050191850 Method for manufacturing semiconductor device
09/01/2005US20050191849 Hydrogen barrier layer and method for fabricating semiconductor device having the same
09/01/2005US20050191848 Removable amorphous carbon CMP stop
09/01/2005US20050191847 Method for manufacturing semiconductor device
09/01/2005US20050191846 Plasma processes for depositing low dielectric constant films
09/01/2005US20050191845 Semiconductor device having a guard ring
09/01/2005US20050191844 Low capacitance wiring layout and method for making same
09/01/2005US20050191843 Fabrication method for semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently
09/01/2005US20050191842 High-aspect-ratio metal-polymer composite structures for nano interconnects
09/01/2005US20050191841 Semiconductor device and wiring forming method in semiconductor device
09/01/2005US20050191840 Method of forming a dual damascene structure
09/01/2005US20050191839 Multiple-ball wire bonds
09/01/2005US20050191838 Apparatus and method for forming bump
09/01/2005US20050191837 Process for producing layer structures for signal distribution
09/01/2005US20050191836 Method to prevent passivation layer peeling in a solder bump formation process
09/01/2005US20050191835 Methods of fabricating semiconductor devices having salicide
09/01/2005US20050191834 Creating shallow junction transistors
09/01/2005US20050191833 Method of fabricating MOS transistor having fully silicided gate
09/01/2005US20050191832 Novel approach to improve line end shortening
09/01/2005US20050191831 Semiconductor device manufacture method capable of supressing gate impurity penetration into channel
09/01/2005US20050191829 Solid material comprising a structure of almost-completely-polarised electronic orbitals, method of obtaining same and use thereof in electronics and nanoelectronics
09/01/2005US20050191826 Germanium deposition
09/01/2005US20050191825 Methods for transferring a thin layer from a wafer having a buffer layer
09/01/2005US20050191824 Methods for producing a multilayer semiconductor structure
09/01/2005US20050191823 Polishing composition and polishing method
09/01/2005US20050191822 Shallow Trench Isolation Method for a Semiconductor Wafer
09/01/2005US20050191821 III-nitride device and method with variable epitaxial growth direction
09/01/2005US20050191820 Method for making improved bottom electrodes for metal-insulator-metal crown capacitors
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