Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2006
06/22/2006US20060134923 Semiconductor substrate cleaning apparatus and method
06/22/2006US20060134922 Method of forming at least one thin film device
06/22/2006US20060134921 Plasma etching process
06/22/2006US20060134920 Exposing the metal surface to a passivation gas, and exposing the freshly etched metal structures to a second particle beam in the presence of the passivation gas; stabilizing metal structures on a substrate such as a semiconductor wafer or photomask; prevents overetching
06/22/2006US20060134919 Processing system and method for treating a substrate
06/22/2006US20060134918 Manufacturing method of substrate having conductive layer and manufacturing method of semiconductor device
06/22/2006US20060134917 Reduction of etch mask feature critical dimensions
06/22/2006US20060134916 Poly open polish process
06/22/2006US20060134915 Polishing apparatus and two-step method of polishing a metal layer of an integrated circuit
06/22/2006US20060134914 Flexible circuits and method of making same
06/22/2006US20060134913 Method for fabricating semiconductor device having stacked-gate structure
06/22/2006US20060134912 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants
06/22/2006US20060134911 MANUFACTURABLE CoWP METAL CAP PROCESS FOR COPPER INTERCONNECTS
06/22/2006US20060134910 Method of forming contact hole and method of fabricating semiconductor device
06/22/2006US20060134909 Method for fabricating semiconductor device
06/22/2006US20060134908 Polishing method
06/22/2006US20060134907 Process for substrate incorporating component
06/22/2006US20060134906 Post-ESL porogen burn-out for copper ELK integration
06/22/2006US20060134905 Multilevel fabrication processing by functional regrouping of material deposition, lithography, and etching
06/22/2006US20060134904 Microelecromechanical system microphone fabrication including signal processing circuitry on common substrate
06/22/2006US20060134903 Connection ball positioning method and device for integrated circuits
06/22/2006US20060134902 Method for constructing contact formations
06/22/2006US20060134901 Hot-Melt Underfill Composition and Methos of Application
06/22/2006US20060134900 Method of forming a metal interconnection line in a semiconductor device using an FSG layer
06/22/2006US20060134899 Method of removing spacers and fabricating mos transistor
06/22/2006US20060134898 Semiconductor damascene trench and methods thereof
06/22/2006US20060134897 Ethyleneoxide-silane and bridged silane precursors for forming low k films
06/22/2006US20060134896 Process for manufacturing liquid ejection head
06/22/2006US20060134895 Method for preparing ge1-x-ysnxey (e=p, as, sb) semiconductors and related si-ge-sn-e and si-ge-e analogs
06/22/2006US20060134894 Method of manufacturing polycrystalline Si film and manufacturing stacked transistor using the same
06/22/2006US20060134893 Fabrication of strained heterojunction structures
06/22/2006US20060134892 Method of enhancing the photoconductive properities of a semiconductor and method of producing a semiconductor with enhanced photoconductive properties
06/22/2006US20060134891 Method for manufacturing semiconductor device
06/22/2006US20060134890 System and process for processing a plurality of semiconductor thin films which are crystallized using sequential lateral solidification techniques
06/22/2006US20060134889 Application of post-pattern resist trim for reducing pocket-shadowing in SRAMs
06/22/2006US20060134888 Method for Cutting Printed Circuit Board
06/22/2006US20060134887 Method of manufacturing a slice of semiconductor
06/22/2006US20060134886 Manufacturing method of semiconductor device
06/22/2006US20060134885 Method of machining substrate and method of manufacturing element
06/22/2006US20060134884 Wafer structure, chip structure, and fabricating process thereof
06/22/2006US20060134883 Systems and methods for electrical contacts to arrays of vertically aligned nanorods
06/22/2006US20060134882 Method to improve device isolation via fabrication of deeper shallow trench isolation regions
06/22/2006US20060134881 Method of forming trench isolation device capable of reducing corner recess
06/22/2006US20060134880 Methods of manufacturing a metal-insulator-metal capacitor
06/22/2006US20060134879 Methods of manufacturing a metal-insulator-metal capacitor
06/22/2006US20060134878 Method of fabricating metal-insulator-metal capacitor
06/22/2006US20060134877 Method for fabricating a buried conductive connection to a trench capacitor and a memory cell with such a connection
06/22/2006US20060134876 SRAM cell
06/22/2006US20060134875 Method of forming storage node of capacitor
06/22/2006US20060134874 Manufacture method of MOS semiconductor device having extension and pocket
06/22/2006US20060134873 Tailoring channel strain profile by recessed material composition control
06/22/2006US20060134872 Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain
06/22/2006US20060134871 Charge-trapping memory device and method of production
06/22/2006US20060134870 Transistor device and method of manufacture thereof
06/22/2006US20060134869 Systems and methods for rectifying and detecting signals
06/22/2006US20060134868 Double gate field effect transistor and method of manufacturing the same
06/22/2006US20060134867 Technique for forming the deep doped columns in superjunction
06/22/2006US20060134866 Non-volatile memory and method for fabricating the same
06/22/2006US20060134865 Method of manufacturing a semiconductor device
06/22/2006US20060134864 Multi-thickness dielectric for semiconductor memory
06/22/2006US20060134863 Methods for reducing wordline sheet resistance
06/22/2006US20060134862 CMOS NVM bitcell and integrated circuit
06/22/2006US20060134861 Semiconductor memory device and method for fabricating the same
06/22/2006US20060134860 Semiconductor processing methods
06/22/2006US20060134859 Mask for forming landing plug contact hole and plug forming method using the same
06/22/2006US20060134858 Method of manufacturing semiconductor device
06/22/2006US20060134857 Memory device and fabrication thereof
06/22/2006US20060134856 Method for manufacturing capacitor of semiconductor element
06/22/2006US20060134855 Method for fabricating capacitor of semiconductor device
06/22/2006US20060134854 Capacitor of semiconductor device and method for forming the same
06/22/2006US20060134853 Standard cell back bias architecture
06/22/2006US20060134852 Interconnect and head gimbal assembly with the same
06/22/2006US20060134851 Method of forming a semiconductor laser chip having a marker
06/22/2006US20060134850 Method of manufacturing a high voltage semiconductor device including a deep well and a gate oxide layer simultaneously
06/22/2006US20060134849 Methods of manufacturing a thin film including zirconium titanium oxide and methods of manufacturing a gate structure, a capacitor and a flash memory device including the same
06/22/2006US20060134848 Method of manufacturing a semiconductor device with mos transistors comprising gate electrodes formed in a packet of metal layers deposited upon one another
06/22/2006US20060134847 Method of manufacturing a SiC vertical MOSFET
06/22/2006US20060134846 Method of fabricating a semiconductor structure
06/22/2006US20060134845 Low-voltage, multiple thin-gate oxide and low-resistance gate electrode
06/22/2006US20060134844 Method for fabricating dual work function metal gates
06/22/2006US20060134843 MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable thickness
06/22/2006US20060134842 Method of fabricating gates
06/22/2006US20060134841 Method of forming pattern having step difference and method of making thin film transistor and liquid crystal display using the same
06/22/2006US20060134840 Electro-optical device and semiconductor circuit
06/22/2006US20060134839 Low voltage non-volatile memory transistor
06/22/2006US20060134838 Processing a memory link with a set of at least two laser pulses
06/22/2006US20060134837 Vertically stacked field programmable nonvolatile memory and method of fabrication
06/22/2006US20060134836 Method of marking a low profile packaged semiconductor device
06/22/2006US20060134835 Method for making a neo-layer comprising embedded discrete components
06/22/2006US20060134834 Packaging substrate and manufacturing method thereof, integrated circuit device and manufacturing method thereof, and SAW device
06/22/2006US20060134833 Packaged semiconductor die and manufacturing method thereof
06/22/2006US20060134832 Manufacturing method of semiconductor device
06/22/2006US20060134831 Integrated circuit packaging using electrochemically fabricated structures
06/22/2006US20060134830 Method and system for performing die attach using a flame
06/22/2006US20060134829 Wafer scale integration of electroplate 3D structures using successive lithography, electroplated sacrifical layers, and flip-chip bonding
06/22/2006US20060134828 Package that integrates passive and active devices with or without a lead frame
06/22/2006US20060134827 Microlenses including a plurality of mutually adhered layers of optically transmissive material and systems including the same
06/22/2006US20060134826 Methods of forming semiconductor packages
06/22/2006US20060134825 Injection-molded package for MEMS inertial sensor
06/22/2006US20060134824 P-type OFET with fluorinated channels