H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2006
10/17/2006	US7122796 Electron beam inspection method and apparatus and semiconductor manufacturing method and its manufacturing line utilizing the same
10/17/2006	US7122780 Exposure apparatus with efficient uniform light output
10/17/2006	US7122777 Image capture device, including methods for arranging the optical components thereof
10/17/2006	US7122748 Semiconductor device having packaging structure
10/17/2006	US7122734 Reduce propagation defects; buffer zone and isoelectric surfactants
10/17/2006	US7122589 Resin having alicyclic hydrocarbon groups in side chains, containing acid; specified two types of repeating units, which increases the solubility in an alkali developing solution by the action of an acid; and (B) a particular
10/17/2006	US7122490 Contains europium calculated as europium oxide; low volume resistivity at room temperature; semiconductors
10/17/2006	US7122489 Manufacturing method of composite sheet material using ultrafast laser pulses
10/17/2006	US7122488 High density plasma process for the formation of silicon dioxide on silicon carbide substrates
10/17/2006	US7122487 Method for forming an oxide with improved oxygen bonding
10/17/2006	US7122486 Film forming method
10/17/2006	US7122485 Deposition profile modification through process chemistry
10/17/2006	US7122484 Process for removing organic materials during formation of a metal interconnect
10/17/2006	US7122482 Methods for fabricating patterned features utilizing imprint lithography
10/17/2006	US7122481 Etching to form a porous interlayer dielectric; bubble vapor deposition of the silane coupling reagent to fill the holes, forming a continuous silica layer over the surface
10/17/2006	US7122480 Method of plasma etching a substrate
10/17/2006	US7122479 Etching processing method
10/17/2006	US7122478 Method of manufacturing a semiconductor device using a polysilicon etching mask
10/17/2006	US7122477 Method of plasma treatment
10/17/2006	US7122476 Method for fabricating semiconductor device by forming trenches in different depths at a cellregion and a peripheral region for reducing self aligned source resistance at the cell region
10/17/2006	US7122475 Methods for using bi-modal abrasive slurries for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies
10/17/2006	US7122474 Method for forming barrier metal of semiconductor device
10/17/2006	US7122473 Edge and bevel cleaning process and system
10/17/2006	US7122472 Method for forming self-aligned dual fully silicided gates in CMOS devices
10/17/2006	US7122471 Method for preventing voids in metal interconnects
10/17/2006	US7122470 Semiconductor device with a CMOS transistor
10/17/2006	US7122469 Fabrication process of a semiconductor integrated circuit device
10/17/2006	US7122468 Methods of fabricating integrated circuit conductive contact structures including grooves
10/17/2006	US7122467 Method for fabricating semiconductor device
10/17/2006	US7122466 Two step semiconductor manufacturing process for copper interconnects
10/17/2006	US7122465 Method for achieving increased control over interconnect line thickness across a wafer and between wafers
10/17/2006	US7122464 Systems and methods of forming refractory metal nitride layers using disilazanes
10/17/2006	US7122463 Manufacturing method of semiconductor device
10/17/2006	US7122462 Back end interconnect with a shaped interface
10/17/2006	US7122461 Forming semiconductor devices from carbon nanotubes which is functionalized with nitric acid, phosphating to bond with deoxyribose nucleic acid (DNA) groups, hybridization to the bondable group on the electrode; microarray chips
10/17/2006	US7122460 Electromigration barrier layers for solder joints
10/17/2006	US7122459 Semiconductor wafer package and manufacturing method thereof
10/17/2006	US7122458 Method for fabricating pad redistribution layer
10/17/2006	US7122457 Semiconductor chip production method, semiconductor device production method, semiconductor chip, and semiconductor device
10/17/2006	US7122456 Method for reduced input output area
10/17/2006	US7122455 Patterning with rigid organic under-layer
10/17/2006	US7122454 Method for improving nitrogen profile in plasma nitrided gate dielectric layers
10/17/2006	US7122453 Methods of patterning radiation, methods of forming radiation-patterning tools, and radiation-patterning tools
10/17/2006	US7122452 Method of manufacturing a semiconductor on a silicon on insulator (SOI) substrate using solid epitaxial regrowth (SPER) and semiconductor device made thereby
10/17/2006	US7122451 Method for fabricating a semiconductor device including exposing a group III-V semiconductor to an ammonia plasma
10/17/2006	US7122450 Process for manufacturing a semiconductor device
10/17/2006	US7122449 Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
10/17/2006	US7122448 Annealing apparatus, annealing method, and manufacturing method of a semiconductor device
10/17/2006	US7122447 Fabrication method of semiconductor circuit device
10/17/2006	US7122446 Semiconductor light-emitting element
10/17/2006	US7122445 Peeling method
10/17/2006	US7122444 Manufacturing method of thin film device substrate
10/17/2006	US7122443 Method of fabricating flash memory device
10/17/2006	US7122442 Method and system for dopant containment
10/17/2006	US7122441 Method of fabricating a plurality of ferroelectric capacitors
10/17/2006	US7122440 Semiconductor device and fabrication method thereof
10/17/2006	US7122439 Method of fabricating a bottle trench and a bottle trench capacitor
10/17/2006	US7122438 Semiconductor memory and method of manufacturing the same
10/17/2006	US7122437 Deep trench capacitor with buried plate electrode and isolation collar
10/17/2006	US7122436 Techniques for forming passive devices during semiconductor back-end processing
10/17/2006	US7122435 Methods, systems and structures for forming improved transistors
10/17/2006	US7122434 Method for generating an electrical contact with buried track conductors
10/17/2006	US7122433 Method for manufacturing trench gate semiconductor device
10/17/2006	US7122432 Non-volatile semiconductor memory device and manufacturing method thereof
10/17/2006	US7122431 Methods of fabrication metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions
10/17/2006	US7122430 Nonvolatile semiconductor memory and manufacturing method for the same
10/17/2006	US7122429 Semiconductor memory and method of manufacturing the same
10/17/2006	US7122428 Device isolation method of semiconductor memory device and flash memory device fabricating method using the same
10/17/2006	US7122427 Method of fabricating non-volatile memory device
10/17/2006	US7122426 Method of fabricating cell of nonvolatile memory device with floating gate
10/17/2006	US7122425 Methods of forming semiconductor constructions
10/17/2006	US7122424 Method for making improved bottom electrodes for metal-insulator-metal crown capacitors
10/17/2006	US7122423 Method for fabricating a memory cell
10/17/2006	US7122422 Methods of forming capacitors
10/17/2006	US7122421 Semiconductor device including a transistor and a capacitor having an aligned transistor and capacitive element
10/17/2006	US7122420 Methods of recessing conductive material and methods of forming capacitor constructions
10/17/2006	US7122419 Capacitor and fabrication method thereof
10/17/2006	US7122418 Method of fabricating organic light emitting diode device
10/17/2006	US7122417 Methods for fabricating metal-oxide-semiconductor field effect transistors using gate sidewall spacers
10/17/2006	US7122416 Method for forming a filled trench in a semiconductor layer of a semiconductor substrate, and a semiconductor substrate with a semiconductor layer having a filled trench therein
10/17/2006	US7122415 Atomic layer deposition of interpoly oxides in a non-volatile memory device
10/17/2006	US7122414 Method to fabricate dual metal CMOS devices
10/17/2006	US7122413 Method to manufacture silicon quantum islands and single-electron devices
10/17/2006	US7122412 Method of fabricating a necked FINFET device
10/17/2006	US7122411 SOI device with reduced drain induced barrier lowering
10/17/2006	US7122410 Polysilicon line having a metal silicide region enabling linewidth scaling including forming a second metal silicide region on the substrate
10/17/2006	US7122409 Semiconductor device and a method of manufacturing the same
10/17/2006	US7122408 Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation
10/17/2006	US7122407 Method for fabricating window ball grid array semiconductor package
10/17/2006	US7122406 Semiconductor device package diepad having features formed by electroplating
10/17/2006	US7122405 Method for packaging chip and package assembly produced thereby
10/17/2006	US7122404 Techniques for packaging a multiple device component
10/17/2006	US7122403 Method of interconnecting die and substrate
10/17/2006	US7122402 Method of manufacturing a semiconductor device using a rigid substrate including the vent-end edge portion of the substrate has a thickness smaller than the other portions of the substrate
10/17/2006	US7122401 Area array type semiconductor package fabrication method
10/17/2006	US7122400 Method of fabricating an interconnection for chip sandwich arrangements
10/17/2006	US7122399 Size reduction of chip mounting system
10/17/2006	US7122398 Manufacturing of optoelectronic devices
10/17/2006	US7122397 Method for manufacturing CMOS image sensor
10/17/2006	US7122396 Semiconductor acceleration sensor and process for manufacturing the same

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